FeRAM capacitor stack etch

ABSTRACT

The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl 3  etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF 3  to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

RELATED APPLICATION

[0001] This application claims priority to Serial No. 60/353,535 filedJan. 31, 2002, which is entitled “FeRAM Capacitor Stack Etch”.

FIELD OF THE INVENTION

[0002] The present invention relates generally to the field ofintegrated circuit processing, and more particularly relates to an FeRAMstructure and a method of manufacture thereof having a capacitor stacketch which effectively etches the ferroelectric dielectric layer withoutdegradation thereof.

BACKGROUND OF THE INVENTION

[0003] Several trends exist, today, in the semiconductor devicefabrication industry and the electronics industry. Devices arecontinuously getting smaller and smaller and requiring less and lesspower. A reason for this is that more personal devices are beingfabricated which are very small and portable, thereby relying on a smallbattery as its supply source. For example, cellular phones, personalcomputing devices, and personal sound systems are devices that are ingreat demand in the consumer market. In addition to being smaller andmore portable, personal devices are requiring more computational powerand on-chip memory. In light of all these trends, there is a need in theindustry to provide a computational device that has a fair amount ofmemory and logic functions integrated onto the same semiconductor chip.Preferably, this memory will be configured such that if the batterydies, the contents of the memory will be retained. Such a memory devicethat retains its contents while a signal is not continuously applied toit is called a non-volatile memory. Examples of conventionalnon-volatile memory include: electrically erasable, programmable readonly memory (“EEPROM”) and FLASH EEPROM.

[0004] A ferroelectric memory (FeRAM) is a non-volatile memory thatutilizes a ferroelectric material, such as SBT or PZT, as the capacitordielectric situated between a bottom electrode and a top electrode. Bothread and write operations are performed for a FeRAM. The memory size andmemory architecture affect the read and write access times of a FeRAM.Table 1 illustrates the differences between different memory types.TABLE 1 FeRAM Property SRAM Flash DRAM (Demo) Voltage >0.5 V Read >1 V3.3 V >0.5 V Write (12 V) (±6 V) Special Transistors NO YES YES NO (HighVoltage) (Low Leakage) Write Time <10 ns 100 ms <30 ns 60 ns WriteEndurance >10¹⁵ <10⁵ >10¹⁵ >10¹³ Read Time (single/ <10 ns <30 ns <30ns/ 60 ns multi bit) <2 ns Read Endurance >10¹⁵ >10¹⁵ >10¹⁵ >10¹³ AddedMask for 0 ˜6-8 ˜6-8 ˜3 embedded Cell Size (F˜metal ˜80 F² ˜8 F² ˜8 F²˜18 F² pitch/2) Architecture NDRO NDRO DRO DRO Non volatile NO YES NOYES Storage I Q Q P

[0005] The non-volatility of an FeRAM is due to the bi-stablecharacteristic of the ferroelectric memory cell. Two types of memorycells are used, a single capacitor memory cell and a dual capacitormemory cell. The single capacitor memory cell (referred to as a 1T/1C or1C memory cell) requires less silicon area (thereby increasing thepotential density of the memory array), but is less immune to noise andprocess variations. Additionally, a 1C cell requires a voltage referencefor determining a stored memory state. The dual capacitor memory cell(referred to as a 2T/2C or 2C memory cell) requires more silicon area,and it stores complementary signals allowing differential sampling ofthe stored information. The 2C memory cell is more stable than a 1Cmemory cell.

[0006] As illustrated in prior art FIG. 1, a 1T/1C FeRAM cell 10includes one transistor 12 and one ferroelectric storage capacitor 14. Abottom electrode of the storage capacitor 14 is connected to a drainterminal 15 of the transistor 12. The 1T/1C cell 10 is read from byapplying a signal to the gate 16 of the transistor (word line WL)(e.g.,the Y signal), thereby connecting the bottom electrode of the capacitor14 to the source of the transistor (the bit line BL) 18. A pulse signalis then applied to the top electrode contact (the plate line or driveline DL) 20. The potential on the bit line 18 of the transistor 12 is,therefore, the capacitor charge divided by the bit line capacitance.Since the capacitor charge is dependent upon the bi-stable polarizationstate of the ferroelectric material, the bit line potential can have twodistinct values. A sense amplifier (not shown) is connected to the bitline 18 and detects the voltage associated with a logic value of either1 or 0. Frequently the sense amplifier reference voltage is aferroelectric or non-ferroelectric capacitor connected to another bitline that is not being read. In this manner, the memory cell data isretrieved.

[0007] A characteristic of the shown ferroelectric memory cell is that aread operation is destructive. The data in a memory cell is thenrewritten back to the memory cell after the read operation is completed.If the polarization of the ferroelectric is switched, the read operationis destructive and the sense amplifier must rewrite (onto that cell) thecorrect polarization value as the bit just read from the cell. This issimilar to the operation of a DRAM. The one difference from a DRAM isthat a ferroelectric memory cell will retain its state until it isinterrogated, thereby eliminating the need of refresh.

[0008] As illustrated, for example, in prior art FIG. 2, a 2T/2C memorycell 30 in a memory array couples to a bit line 32 and an inverse of thebit line (“bit line-bar”) 34 that is common to many other memory types(for example, static random access memories). Memory cells of a memoryblock are formed in memory rows and memory columns. The dual capacitorferroelectric memory cell comprises two transistors 36 and 38 and twoferroelectric capacitors 40 and 42, respectively. The first transistor36 couples between the bit line 32 and a first capacitor 40, and thesecond transistor 38 couples between the bit line-bar 34 and the secondcapacitor 42. The first and second capacitors 40 and 42 have a commonterminal or plate (the drive line DL) 44 to which a signal is appliedfor polarizing the capacitors.

[0009] In a write operation, the first and second transistors 36 and 38of the dual capacitor ferroelectric memory cell 30 are enabled (e.g.,via their respective word line 46) to couple the capacitors 40 and 42 tothe complementary logic levels on the bit line 32 and the bar-bar line34 corresponding to a logic state to be stored in memory. The commonterminal 44 of the capacitors is pulsed during a write operation topolarize the dual capacitor memory cell 30 to one of the two logicstates.

[0010] In a read operation, the first and second transistors 36 and 38of the dual capacitor memory cell 30 are enabled via the word line 46 tocouple the information stored on the first and second capacitors 40 and42 to the bar 32 and the bit line-bar line 34, respectively. Adifferential signal (not shown) is thus generated across the bit line 32and the bit line-bar line 34 by the dual capacitor memory cell 30. Thedifferential signal is sensed by a sense amplifier (not shown) thatprovides a signal corresponding to the logic level stored in memory.

[0011] A memory cell of a ferroelectric memory is limited to a finitenumber of read and write operations before the memory cell becomesunreliable. The number of operations that can be performed on a FeRAMmemory is known as the endurance of a memory. The endurance, is animportant factor in many applications that require a nonvolatile memory.Other factors such as memory size, memory speed, and power dissipationalso play a role in determining if a ferroelectric memory is viable inthe memory market.

SUMMARY OF THE INVENTION

[0012] In essence, the instant invention relates to the fabrication ofan FeRAM device which is either a stand-alone device or one which isintegrated onto a semiconductor chip which includes many other devicetypes. Several requirements either presently exist or may becomerequirements for the integration of FeRAM with other device types. Onesuch requirement involves utilizing, as much as possible, theconventional front end and back end processing techniques used forfabricating the various logic and analog devices on the chip tofabricate this chip which will include FeRAM devices. In other words, itis beneficial to utilize as much of the process flow for fabricatingthese standard logic devices (in addition to I/O devices and potentiallyanalog devices) as possible, so as not to greatly disturb the processflow (and thus increase the process cost and complexity) merely tointegrate the FeRAM devices onto the chip.

[0013] The following discussion is based on the concept of creating theferroelectric capacitors in a FeRAM process module that occurs betweenthe front end module (defined to end with the formation of W contacts)and the back end process module (mostly metallization). Other locationsof the FeRAM process module have also been proposed. For example, if theFeRAM process module is placed over the first layer of metallizationthen a capacitor over bar structure can be created with the advantagethat a larger capacitor can be created. One disadvantage of the approachis that either Metal-1 or a local interconnect must be compatible withFeRAM process temperature (W for example) or the FeRAM processtemperature must be lowered to be compatible with standard metallization(Al˜450 C., Cu-Low-K˜400 C.). This location has some advantages forcommodity memory purposes, but has cost disadvantages for embeddedmemory applications. Another proposed location for the FeRAM processmodule is near the end of the back end process flow. The principaladvantage of this approach is that it keeps new contaminants in theFeRAM module (Pb, Bi, Zr, Ir, Ru, or Pt) out of more production tools.This solution is most practical if the assumption is that all of theequipment used after deposition of the first FeRAM film must bededicated and cannot be shared. This solution has the drawback ofrequiring FeRAM process temperatures compatible with standardmetallization plus wiring of the FeRAM capacitor to transistor and otherneeds of metallization are not compatible with a minimum FeRAM cellsize.

[0014] The requirements for the other locations will have many of thesame concerns, but some requirements will be different.

[0015] The FeRAM process module must therefore be compatible withfront-end process flow including the use of W contacts (currentlystandard in most logic flows) as the bottom contact of the capacitor.The FeRAM thermal budget must also be low enough so that it does notimpact the front-end structures such as the low resistance structures(such as tungsten plugs and silicided source/drains and gates) requiredby most logic devices. In addition, transistors and other front-enddevices such as diodes are sensitive to contamination and the FeRAMprocess module cannot contaminate these devices either directly(diffusion in chip) or indirectly (cross contamination through sharedequipment). The FeRAM devices and process module must also be compatiblewith a standard back end process flow. Therefore the FeRAM processmodule must have minimum degradation of logic metallization resistanceand parasitic capacitance between metal and transistor. In addition, theFeRAM devices must not be degraded by the back end process flow withminimal, if any, modification. This is a significant challenge sinceferroelectric capacitors have been shown to be sensitive to hydrogendegradation and most logic back end process flows use hydrogen/deuteriumin many of the processes (SiO₂, Si₃N₄, and CVD W deposition, SiO₂ viaetch, and forming gas anneals).

[0016] Commercial success of FeRAM also requires minimization ofembedded memory cost. Total memory cost is primarily dependent on cellsize, periphery ratio size, impact of yield, and additional processcosts associated with memory. In order to have a cost advantage per bitcompared to standard embedded memories such as embedded DRAM and Flashit is necessary to have cell sizes that are not much larger than thesecompeting technologies. Some of the methods discussed in this patent tominimize cell size is to make the process flow less sensitive tolithography misalignment, have the capacitor directly over the contact,and using a single mask for the capacitor stack etch.

[0017] In accordance with one aspect of the present invention, a methodof forming an FeRAM capacitor is provided in which the etching of theferroelectric capacitor stack is greatly improved. The method comprisesan etch of the capacitor stack using a patterning hard mask, forexample, a TiAlN hard mask. An etch of the PZT ferroelectric layerduring the capacitor stack etch comprises a BCl₃ etch at a substantiallyhigh temperature, for example, about 150° C. or more (e.g., 350° C.).Surprisingly, the BCl₃ PZT etch at a relatively high temperature issubstantially selective with respect to the overlying patterned hardmask, thereby providing a quality etched PZT film without substantialhard mask erosion, thereby resulting in good critical dimension controlof the capacitor stack.

[0018] In accordance with another aspect of the present invention, thecapacitor stack comprises iridium top and bottom electrode layers, and aPZT ferroelectric layer disposed between the top and bottom electrodelayers. A nitride hard mask, for example, TiAlN, is formed and patternedover the capacitor stack layers. A Cl₂+O₂ or a Cl₂+CO etch is employedto pattern the top electrode layer, wherein the oxygen content thereinhelps provide a substantial etch selectivity with respect to the hardmask. The PZT layer is then etched with a BCl₃ etch at a temperature ofat least about 150° C. Unexpectedly, the high temperature BCl₃ etchprovides good selectivity with respect to the hard mask despite the factthat no oxygen is provided during such etch, thereby providing for ahigh quality etched PZT film without substantial erosion of the hardmask. Accordingly, a minimal capacitor stack critical dimension ismaintained. The bottom electrode is then etched in a manner similar tothat of the top electrode layer.

[0019] In accordance with another aspect of the present invention, acapacitor stack etch is disclosed in which a sidewall profile of the PZTferroelectric layer is made non-vertical. Use of a sloped ornon-vertical PZT sidewall profile is not obvious because typicallyvertical or closely vertical sidewalls are desired to minimize thecritical dimension of the capacitor. The PZT sidewall profile is madenon-vertical (e.g., less than about 88 degrees) in order to facilitateion impingement thereon during the subsequent etch of the bottomelectrode layer. The ion impingement (e.g., chlorine ions) on the slopedPZT sidewall during the bottom electrode layer etch ensures thatre-deposition of conductive bottom electrode material onto the PZTsidewall does not occur by having the removal rate thereof be greaterthan the deposition rate due to re-sputtering. Accordingly, after thebottom electrode etch, no bottom electrode material resides on the PZTsloped sidewall, thereby preventing leakage or a shorting out of theFeRAM capacitor.

[0020] In accordance with still another aspect of the present invention,a capacitor stack etch having a sloped PZT sidewall profile comprisesetching the PZT layer with a fluorine+Cl₂+oxidizer etch chemistry at alow temperature, for example, about 60° C. The low temperature causesthe sidewall profile of the PZT to not be vertical (a non-anisotropicetch). In addition, the low PZT etch temperature surprisingly eliminatesgaps or voids in the PZT ferroelectric layer that occurred with fluorinecontaining etch chemistries at high temperatures. In one particularexample, the PZT etch comprises a CHF₃+Cl₂+O₂+N₂ at a temperature ofabout 60° C., resulting in a PZT sidewall profile of less than about 88degrees. A PZT sidewall angle of less than 88 degrees is sufficient toensure no net deposition of conductive material thereon during thesubsequent patterning of the underlying bottom electrode layer.

[0021] To the accomplishment of the foregoing and related ends, theinvention comprises the features hereinafter fully described andparticularly pointed out in the claims. The following description andthe annexed drawings set forth in detail certain illustrative aspectsand implementations of the invention. These are indicative, however, ofbut a few of the various ways in which the principles of the inventionmay be employed. Other objects, advantages and novel features of theinvention will become apparent from the following detailed descriptionof the invention when considered in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is a prior art schematic diagram illustrating an exemplary1T/1C FeRAM memory cell;

[0023]FIG. 2 is a prior schematic diagram illustrating an exemplary2T/2C FeRAM memory cell;

[0024]FIG. 3 is a fragmentary cross-sectional view of a partiallyfabricated device containing FeRAM capacitors and transistors associatedtherewith fabricated in accordance with one exemplary aspect of thepresent invention;

[0025]FIG. 4 is a flow chart diagram illustrating a method of forming anFeRAM capacitor in accordance with another exemplary aspect of thepresent invention;

[0026]FIGS. 5 and 6 are fragmentary cross-sectional views of twoneighboring FeRAM capacitor stacks having a bottom electrode diffusionbarrier layer etched and a result thereof;

[0027]FIG. 7 is a schematic diagram illustrating an apparatus forforming a PZT ferroelectric film in accordance with the presentinvention;

[0028] FIGS. 8-11 are graphs illustrating various performancecharacteristics of a PZT ferroelectric film formed in accordance withthe present invention;

[0029]FIGS. 12 and 13 are fragmentary cross section diagramsillustrating how an etch of the bottom electrode diffusion barrier layercauses a rounding of the hard mask layer which may cause a contaminationof a top electrode layer;

[0030]FIG. 14 is a flow chart diagram illustrating a method of forming amulti-layer hard mask layer in accordance with the present invention;

[0031]FIGS. 15a and 15 b are fragmentary cross section diagramsillustrating steps in etching the bottom electrode diffusion barrierlayer using a multi-layer hard mask according to the present invention;

[0032]FIG. 16 is a flow chart diagram illustrating a method of formingan FeRAM capacitor wherein a sidewall diffusion barrier layer isdeposited and selectively patterned prior to the patterning of thebottom electrode diffusion barrier layer according to the presentinvention;

[0033]FIGS. 17 and 18 are fragmentary cross section diagramsillustrating steps in depositing and selectively patterning a sidewalldiffusion barrier layer prior to patterning a bottom electrode diffusionbarrier layer according to the present invention;

[0034]FIG. 19 is a fragmentary cross section diagram illustrating anetch of the bottom electrode diffusion barrier layer after thedeposition and patterning of the sidewall diffusion barrier layeraccording to the present invention; and

[0035]FIGS. 20 and 21 are fragmentary cross section diagramsillustrating how identification of aluminum oxide “ears” are employed toascertain whether the sidewall diffusion barrier layer is sufficientlythick on sidewalls of FeRAM capacitors stacks according to the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0036] The present invention will now be described with respect to theaccompanying drawings in which like numbered elements represent likeparts. While the following description of the instant invention revolvesaround the integration of the FeRAM devices with logic devices and otherdevices which can be found on a digital signal processor,microprocessor, smart card, microcomputer, microcontroller or system ona chip, the instant invention can be used to fabricate stand-alone FeRAMdevices or FeRAM devices integrated into a semiconductor chip which hasmany other device types. In particular, the improved performance of theFeRAM device of the instant invention compared to standard semiconductormemories appears to make FeRAM the memory of choice for any handhelddevice which requires low power and large degree of device integration.

[0037] The figures provided herewith and the accompanying description ofthe figures are provided for illustrative purposes. One of ordinaryskill in the art should realize, based on the instant description, otherimplementations and methods for fabricating the devices and structuresillustrated in the figures and in the following description. Forexample, while shallow trench isolation structures (“STI”) areillustrated, any conventional isolation structures may be used, such asfield oxidation regions (also known as LOCOS regions) or implantedregions. In addition, while structure 102 is preferably a single-crystalsilicon substrate that is doped to be n-type or p-type structure 102(FIG. 3) may be formed by fabricating an epitaxial silicon layer on asingle-crystal silicon substrate.

[0038] In accordance with the present invention, a plurality of methodsare disclosed which decrease a reduction of an iridium oxide bottomelectrode during a subsequent formation of a ferroelectric dielectriclayer in an FeRAM capacitor. By decreasing a reduction of the iridiumoxide bottom electrode, a fatigue resistance of the FeRAM cell isimproved substantially over the prior art.

[0039] Referring initially to FIG. 3, an exemplary, fragmentary crosssection of a semiconductor device 100 is provided in which two devicesare illustrated. A first device 103 represents a partially fabricatedversion of am FeRAM cell in accordance with the present invention, and asecond device 105 represents any high-voltage transistor, low-voltagetransistor, high-speed logic transistor, I/O transistor, analogtransistor, or any other device which may be included in a digitalsignal processor, microprocessor, microcomputer, microcontroller or anyother semiconductor device. Except for the specific cell structureprovided in the device 103, the structures utilized therein may be thesame as the device structures of the device 105 (except for somepossible variations in the transistors due to the-different device typesthat device 105 may be).

[0040] Basically, gate structures 106 include a gate dielectric (forexample, comprising silicon dioxide, an oxynitride, a silicon nitride,BST, PZT, a silicate, any other high-k material, or any combination orstack thereof), a gate electrode (for example, comprisingpolycrystalline silicon doped either p-type or n-type with a silicideformed on top, or a metal such as titanium, tungsten, TiN, tantalum, TaNor other type metal). The gate structures 106 further comprise sidewallinsulators (for example, comprising an oxide, a nitride, an oxynitride,or a combination or stack thereof). In general, the generic terms oxide,nitride and oxynitride refer to silicon oxide, silicon nitride andsilicon oxy-nitride. The term “oxide” may, in general, include dopedoxides as well, such as boron and/or phosphorous-doped silicon oxide.Source/drain regions 108 may be formed via, for example, implantationusing conventional dopants and processing conditions. Lightly dopeddrain extensions 109 as well as pocket implants may also be utilized. Inaddition, the source/drain regions 108 may be silicided (for example,with titanium, cobalt, nickel, tungsten or other conventional silicidematerial).

[0041] A dielectric layer 112 is formed over the entire substrate 102and is patterned and etched so as to form openings for contacts to thesubstrate and gate structures 106 to be formed (see, e.g., step 202 ofFIG. 4). These openings are filled subsequently with one or moreconductive materials, such as a plug 114 (for example, comprising ametal such as tungsten, molybdenum, titanium, titanium nitride, tantalumnitride, or a metal silicide such as Ti, Ni or Co, copper or dopedpolysilicon). A liner/barrier layer 116 may or may not be formed betweenthe plug 114 and dielectric 112. Such a liner/barrier layer 116 isillustrated in FIG. 3 and comprises, for example, Ti, TiN, TaSiN, Ta,TaN, TiSiN, a stack thereof, or any other conventional liner/barriermaterial. Preferably, the contacts are formed so as to land on thesilicided regions of the source/drain regions and gate structures.

[0042] The dielectric layer 112 comprises, for example, SiO₂ (doped orundoped with preferable dopants such as boron or phosphorous) possiblywith a layer of hydrogen or deuterium containing silicon nitride next tothe gate. After deposition of the diffusion barrier 116 it is likelythat the barrier will be planarized for improved lithography ofoverlying layers using a process such as chemical mechanical polishing(CMP). In addition, an added diffusion barrier/etch stop (not shown) maybe included near the top surface of layer 112 such as AlO_(X), AlN,Si₃N₄, TiO₂, ZrO₂, or TaO_(X) that would be deposited after theplanarization process. This diffusion barrier is particularly useful ifdamascene processes are used to create the via or metallization to thecontact. The formation of the plug 114 will require etching through thisoptional barrier/etch stop.

[0043] Formation of metal structures that are situated above thecontacts is considered to be part of the back end processes. Other thanthe specific FeRAM process module, the back end process steps may bethose standard in the semiconductor industry. The metallization may be,for example, either Al or Cu based. The Al is preferably etched whilethe Cu is preferably used in a damascene approach. However, etching Cuand Al formed in a damascene process is also possible. According to oneexample, aluminum metallization will preferably have CVD tungsten plugsor Al plugs, and the Al will preferably be Cu-doped for improvedelectromigration resistance. Metal diffusion barriers for Al mayinclude, for example, TiN and/or Ti. Copper metallization may have, forexample, Cu or W plugs with either Ti, TiN, TiSiN, Ta, tantalum nitride,and/or TaSiN diffusion barriers.

[0044] A thin dielectric layer (not shown) may be formed between each ofthe interlevel dielectric (ILD) layers (layers 112, 134 and 160). Ifformed, this thin dielectric comprises, for example, silicon nitride,silicon carbide, SiCNO or a silicon oxide (for example, a high-densityplasma oxide). In addition, interlevel dielectric layers 112, 134, and160 may comprise, for example, an oxide, FSG, PSG, BPSG, PETEOS, HDPoxide, a silicon nitride, silicon oxynitride, silicon carbide, siliconcarbo-oxy-nitride, a low dielectric constant material (for example,SiLK, porous SiLK, teflon, low-K polymer (possibly porous), aerogel,xerogel, BLACK DIAMOND, HSQ, or any other porous glass material), or acombination or stack thereof.

[0045] The interconnects and the metal lines preferably comprise thesame material. Plugs 136 and 150 and conductors 144 and 164 comprise ametal material (for example, copper, aluminum, titanium, TiN, tungsten,tungsten nitride, or any combination or stack thereof). A barrier/linermay be formed between the plug and the respective interlevel dielectriclayer. If formed, the barrier/liner layer (shown as layers 138 and 148and liners 142, 146, 162 and 166) comprises, for example, Ti, TiN, W,tungsten nitride, Ta, tantalum nitride, any conventional barrier/linerlayer, or any combination or stack thereof). The interlayer dielectricand plug material should be compatible with the FeRAM thermal budget.With existing technology (i.e., one that incorporates a W plug and SiO₂ILD), the FeRAM thermal budget should be less than approximately 600 or650 C., however, the present invention is not limited thereto. If theILD is modified to include a low dielectric constant (“low K”) layer,the FeRAM thermal budget may need to be reduced further. The preferredinterlayer dielectric 112 is therefore a material that can withstand athermal budget in excess of 600 C., such as silicon oxide (doped and/orundoped), silicon nitride, and/or silicon oxy-nitride.

[0046] Level 127 is added so as to accommodate the FeRAM cells (FeRAMprocess module). This FeRAM process module allows the creation offerroelectric or high dielectric constant capacitors to be easily addedwith maximum thermal budget for the new process module yet not impactthe thermal budget of backend process. In particular, this level allowsFeRAM devices with capacitor under bit line configuration compatiblewith a high-density memory. However, it is possible, if planarity is nota necessity, to form the FeRAM devices while not forming layer 127 inregion 105. Hence, the FeRAM portion 103 would be taller than the region105 by the height of layer 127.

[0047] Initially, a further discussion of FIG. 3 will be provided toappreciate the structure of an FeRAM cell and an exemplary integrationposition of such a cell within a semiconductor fabrication process.Subsequently, a flow chart and a number of fragmentary cross sectiondiagrams will be provided to illustrate an exemplary process forfabricating such an FeRAM cell in order to provide a context in whichthe present invention may reside. In conjunction therewith, the presentinvention will be described and illustrated in greater detail. It shouldbe understood, however, that although the present invention will beshown and described in conjunction with one exemplary context, theinvention is applicable to other fabrication methodologies, structuresand materials, and such alternatives are contemplated as falling withinthe scope of the present invention.

[0048] An FeRAM capacitor, as illustrated in FIG. 3 at reference numeral125, resides above the interlayer dielectric 112, and comprises severallayers. The FeRAM capacitor 125 of FIG. 3 comprises an electricallyconductive barrier layer 122 upon which a conductive bottom capacitorelectrode 124 resides (hereinafter, the terms conductive and insulativeare employed to indicate electrically conductive and electricallyinsulative, respectively, unless indicated otherwise). A capacitordielectric layer 126, a ferroelectric material, is formed over thebottom electrode 124, and is covered by, for example, a conductivemulti-layer top electrode 128, 130. A top portion of the FeRAM capacitor125 comprises a hard mask layer 132 that, as will be discussed ingreater detail later, may be employed to facilitate the capacitor stacketch. The capacitor stack is then covered by a multi-layer sidewalldiffusion barrier 118, 120.

[0049] An exemplary method of forming an FeRAM capacitor in accordancewith the present invention which is similar in many respects to thecapacitor 125 of FIG. 3 will now be discussed in conjunction with FIGS.4, wherein a method 200 of forming an FeRAM capacitor is disclosed. At202, the interlevel dielectric 112 is formed and conductive contacts,for example, tungsten (W) contacts 114 are formed therein with a barrierlayer 116 (e.g., TiN) disposed therebetween to avoid oxidation of thetungsten contacts. Formation of the interlayer dielectric 112 and thecontacts 114 may be formed by various means and any such process iscontemplated as falling within the scope of the present invention. Thenthe FeRAM capacitor(s) are formed over the interlayer dielectric 112 andthe contacts 114, as illustrated in FIG. 3.

[0050] According to one aspect of the present invention, once theinterlayer dielectric 112 and the tungsten contacts 114 are formed, theFeRAM capacitor formation process begins. According to one prior artfabrication technique, a bottom electrode was formed directly over theinterlayer dielectric, however, the bottom electrode material, forexample, an iridium or an iridium/iridium oxide multi-layer would notprovide a sufficient diffusion barrier (e.g., oxygen or hydrogen) duringsubsequent processing. That is, during the subsequent formation of theferroelectric dielectric, for example, oxygen may diffuse through thebottom electrode and cause the tungsten to oxidize, thus increasingdisadvantageously a resistance between the contact and the FeRAMcapacitor. One solution to the above problem is to increase a thicknessof the bottom electrode. Since a bottom electrode material acts in somefashion as a diffusion barrier, by increasing the thickness thereof,less diffusion would pass therethrough. Such a solution, however,disadvantageously increases the thickness of the FeRAM capacitor thatpreferably is as thin as possible.

[0051] In order to overcome the above disadvantages, another prior artsolution provided a dedicated bottom electrode diffusion barrier layer.Such a barrier layer is formed over the interlayer dielectric and thetungsten contact prior to the formation of the bottom electrode. Such abarrier is electrically conductive and serves to provide an effectivediffusion barrier without having to increase a thickness of the bottomelectrode. Since the diffusion barrier is a more efficient barrier thanthe bottom electrode material(s), even though the additional barrier isemployed, the net thickness is less than would otherwise be required ifthe bottom electrode material was increased to provide an equivalentbarrier performance. The prior art bottom electrode diffusion barriermaterial was TiAlN, and was formed via physical vapor deposition.

[0052] The prior art TiAlN diffusion barrier provides an effectivebarrier for diffusion of materials such as oxygen and hydrogen. Aproblem has been discovered by the inventors of the present inventionthat the TiAlN material is a source of integration problems duringsubsequent processing of the FeRAM capacitor. More particularly, it wasdiscovered that during subsequent processing of the FeRAM capacitorstack (via etching), an etching of the TiAlN barrier layer betweenneighboring FeRAM capacitor cells caused a substantial undercutting ofthe TiAlN beneath the capacitor stack and such phenomena negativelycontributed to poor step coverage of a subsequently formed electricallyinsulating FeRAM sidewall diffusion barrier. Consequently, the overalldiffusion barrier (top, bottom and sidewalls) of the FeRAM capacitor iscompromised. In order to fully appreciate the problem associatedtherewith, a discussion of the FeRAM capacitor stack etch will bediscussed in conjunction with FIGS. 5-6.

[0053] After the TiAlN bottom electrode diffusion barrier layer 122 isformed, the bottom electrode layer 124, the ferroelectric dielectriclayer 126, the top electrode layer 128, 130, and a hard mask layer 132are deposited and subsequently etched using the hard mask to self-alignone or more FeRAM capacitor stacks 220, as illustrated in FIG. 5. TheTiAlN bottom electrode diffusion barrier 122 also needs to be etchedbecause TiAlN is electrically conductive and without further etching,the barrier layer 122 would short the neighboring capacitors together.

[0054] An etch of the exposed TiAlN barrier 122 between neighboringFeRAM capacitor stacks is performed typically using a dry, chlorinebased etch and ideally would be anisotropic. However, the inventors havenoted that the chlorine etch has a significant chemical component thatcauses the etch to be relatively isotropic, resulting in an undercuttingof the FeRAM stacks, as illustrated in FIG. 6. Although such an undercutwould not appear to negatively impact the capacitor performance, it hasbeen discovered that such undercutting negatively impacts the stepcoverage of a subsequently deposited sidewall diffusion barrier (notshown). Consequently, the TiAlN barrier layer 122, due to integrationproblems, results in degradation in the subsequently formed sidewalldiffusion barrier, thereby negatively impacting the capacitorperformance.

[0055] The inventors of the present invention have overcome thedifficulties of the problem highlighted above by replacing the TiAlNbarrier layer with a TiAlON barrier layer at 204 of FIG. 4. Such areplacement, however, is not a mere substitution of another materialbecause one of ordinary skill in the art would not be motivated to addoxygen because such an addition increases the electrical resistance ofthe resulting layer. As discussed previously, it is desirable to keepthe resistance of the barrier layer as low as possible to thereby reducethe resistance between the bottom electrode of the FeRAM capacitor andthe underlying transistor through the tungsten contact. The inventors ofthe present invention, however, discovered that by adding a small amountof oxygen, one could obtain a substantial reduction in the isotropy ofthe chlorine etch without substantially increasing a resistivity of thebarrier layer, that is, increasing the resistivity above a predeterminedlevel.

[0056] According to one exemplary aspect of the present invention, thecomposition of the TiAlON is tuned to provide sufficient aluminumtherein for adequate oxidation resistance (of the underlying tungstencontact(s)) and enough oxygen to prevent undercutting during an etchthereof, yet concurrently maintaining the resistivity thereof low enoughto prevent any appreciable degradation of the electrical performance ofthe circuit. In one example, the aluminum composition is at least about20 cation atom %, and less than about 50 cation atom %; and the oxygencomposition is at least about 5 anion atom %, and less than about 50anion atom %. In another example, the aluminum composition is at leastabout 35 cation atom %, and less than about 45 cation atom %; and theoxygen composition is at least about 10 anion atom %, and less thanabout 20 anion atom %.

[0057] In accordance with one exemplary aspect of the present invention,it is desirable to have a barrier resistivity of about 4300 μΩ-cm orless. Therefore in tailoring the TiAlON bottom electrode diffusionbarrier film, it is desired to keep the amount of oxygen thereinsufficiently low such that the resistivity does not exceed substantiallythe 4300 μΩ-cm figure. For example, with a TiAlON content of aboutTi≈0.5, Al≈0.4, O≈0.1, and N≈0.9, a film resistivity of about 1800 μΩ-cmwas obtained. Such a TiAlON film is formed, for example, via a PVD orsputter deposition process using an Endura TTN™ chamber with a heatertemperature of 400 C., Ar heater 15 sccm, Ar chamber 56 sccm, O₂ chamber9 sccm, cryo pump. In addition, with such a barrier, experimental testsindicate that the etch rate is about 150 nm/min using a BCl₃+Cl₂chemistry and is about 15 nm/min with solely Cl₂, compared to a TiAlNetch rate of about 300 nm/min. Consequently, the TiAlON barrier of thepresent invention provides a substantial reduction in etch isotropy withan acceptable increase in resistivity.

[0058] In addition, another alternative method of forming the TiAlONfilm is via MOCVD using TiAlN (creating TiAICON). The composition istuned in order to obtain enough Al for oxidation resistance and enoughoxygen for etch undercut yet keeping the resistance low enough so as notto degrade the electrical performance.

[0059] The inventors of the present invention also ascertained that theCMP process used to planarize the interlayer dielectric 112 and thetungsten contact 114 generates seams in the tungsten contact. Most seamsare about 200-400 Angstroms in diameter and are adequately filled by thesubsequently formed barrier layer, for example, TiAlN. However, a smallpercentage of such seams are substantially larger, for example, about600-800 Angstroms in diameter. With such larger seams, the conventionalbarrier layer, formed via physical vapor deposition (PVD), does notadequately fill the seam due to necking, for example. Such poor seamcoverage may undesirably increase the contact resistance between theunderlying transistor and the FeRAM capacitor.

[0060] In accordance with one aspect of the present invention, the largeseams in the tungsten contact 114 are addressed by making the diffusionbarrier layer a multi-layer, with a first layer of TiN formed over theinterlayer dielectric 112 and the tungsten contact 114 via chemicalvapor deposition (CVD). Due to the CVD process, the TiN exhibitsexemplary step coverage, thus filling in a portion of any large seams inthe tungsten contacts. For example, a TiN layer of about 100 Angstromsreduces a seam having a diameter of about 600 Angstroms to about 400Angstroms. Since a CVD TiN process is employed as the contact barrierfor tungsten contacts, the well-developed and characterized process maybe employed readily for such a first layer barrier. The second layer ofthe multi-layer barrier is then formed over the CVD TiN, for example, aTiAlN film or a TiAlON film for the reasons highlighted above. Becausethe TiN layer has reduced the size of any large seams, the second layer(formed via PVD, for example) easily fills the reduced size seam, andaccordingly any potential increase in resistivity due to the seam issubstantially eliminated.

[0061] Therefore in accordance with one aspect of the present invention,the bottom electrode diffusion barrier comprises a bi-layer process. Forexample, first a CVD TiN film is formed having a thickness of about 40nm, followed by a PVD TiAlN film of about 30 nm. In accordance with oneexemplary aspect of the present invention, the TiAlN have at least about30% aluminum, and less than about 60% . Alternatively, the TiAlN has atleast about 40% aluminum, and less than about 50% in order to exhibitimproved oxidation resistance.

[0062] In the above example, TiAlN is discussed as one form of diffusionbarrier in conjunction with the initial TiN layer. Alternatively, aTiAlON layer as discussed above may be utilized in conjunction with theTiN; and other diffusion barrier layers may be employed, for example,TaSiN, TiSiN, TaAlN, Ti, TiN, Ta, TaN, HfN, ZrN, HfAlN, CrN, TaAlN,CrAlN. The preferred deposition technique for these barrier layers is areactive sputter deposition using Ar+N₂ or Ar+NH₃. Other depositiontechniques that might be used include CVD or plasma enhanced CVD. In anyevent, it is preferred to use materials that have a slower oxidationrate than TiN.

[0063] In addition to the discussion above regarding the diffusionbarrier layer, it is desirable to perform a clean operation of theinterlayer dielectric 112 and the tungsten contact 114 prior to thedeposition of the barrier layer. For example, one option is to sputterclean with Ar prior to the deposition of the barrier layer. It isfurther preferred that this pre-clean occur without a vacuum break priorto the deposition of the barrier.

[0064] The next layer is the oxygen stable bottom electrode 124, asillustrated at 206 of FIG. 4. This layer needs to be stable during thesubsequent deposition of the ferroelectric and can strongly impact theproperties of the ferroelectric capacitor. For example, with a PZTferroelectric the reliability is improved with oxide electrodes. Theelectrode experiences the thermal budget and oxidizing conditions of theferroelectric deposition and possibly anneal. Therefore the bottomelectrode preferably is stable in oxygen and does not form insulatinglayers as a result of such oxygen. It is also advantageous that thebottom electrode at least partially impedes the oxidation and reactionof the underlying diffusion barrier.

[0065] In addition, the electrode preferably maintains a relatively lowcontact resistance. A list of possible materials includes Pt, Pd, PdOx,IrPt alloys, Au, Ru, RuO_(x), (Ba,Sr,Pb)RuO3, (Sr,Ba,Pb)IrO3, Rh,RhO_(x), LaSrCoO₃, (Ba,Sr)RuO₃, LaNiO₃.

[0066] The bottom electrode 124 of the capacitor is formed either withor without the barrier layer 122 so as to make electrical connectionwith the underlying contact structure 114. Preferably, the bottomelectrode 124 is around 30-100 nm thick, is stable in oxygen and iscomprised of a noble metal or conductive oxide such as iridium, iridiumoxide, Pt, Pd, PdOx, Au, Ru, RuO_(x), Rh, RhO_(x), LaSrCoO₃,(Ba,Sr)RuO₃, LaNiO₃ or any stack or combination thereof. For anyelectrode using noble metals it is advantageous from a cost and ease ofintegration standpoint to use layer as thin as possible.

[0067] For a PZT dielectric, it is preferred to have an oxide electrodesuch as IrOx in contact therewith at the top and/or bottom electrode. Inaddition, it is preferred to have a noble metal between the conductiveoxide electrode and either the top or bottom diffusion barrier. Thenoble metal prevents oxidation of the diffusion barrier and theresulting formation of an insulating layer that increases undesirablythe contact resistance. The preferred thickness of this noble metallayer is 10-30 nm. Thus in one aspect of the invention, the bottomelectrode 124 comprises an Ir/IrO₂ sandwich.

[0068] The preferred bottom electrode for PZT is either 50 nm Irdeposited by sputter deposition for Ir (Ar) and/or reactive sputterdeposition (Ar+O₂) for IrOx. A second preferred electrode stack uses 10nm Ir on 30 nm IrOx on 20 nm Ir (one potential thickness is shown). Athird preferred embodiment is IrOx (˜30-40 nm) on Ir (20-30 nm). Thepreferred deposition technique for these layers is sputter or reactivesputter deposition or chemical vapor deposition.

[0069] The capacitor dielectric 126 is formed on the bottom electrode124, as illustrated at 208 of FIG. 4. Preferably, the capacitordielectric is less than 150 nm thick (more preferably less than 100 nmthick-most preferably less than 50 nm thick) and is comprised of aferroelectric material, such as Pb(Zr,Ti)O₃ PZT (lead zirconatetitanate), doped PZT with donors (Nb, La, Ta) acceptors (Mn, Co, Fe, Ni,Al) and/or both, PZT doped and alloyed with SrTiO3, BaTiO3 or CaTiO3,strontium bismuth tantalate (SBT) and other layered perovskites such asstrontium bismuth niobate tantalate (SBNT) or bismuth titanate, BaTiO3,PbTiO3,Bi2TiO3 etc.

[0070] PZT is a desirable choice for the capacitor dielectric because ithas the highest polarization and the lowest processing temperature ofthe aforementioned materials. Thin PZT (<100 nm) is extremelyadvantageous in making integration more simple (less material to etch)and less expensive (less material to deposit therefore less precursor).Because PZT has the largest switched polarization, it is also possibleto minimize capacitor area using such material.

[0071] The preferred deposition technique for these dielectrics is metalorganic chemical vapor deposition (MOCVD). MOCVD is preferred especiallyfor thin films (<100 nm). MOCVD also permits the film thickness to bescaled without significant degradation of switched polarization andcoercive field, yielding PZT films with a low operating voltage andlarge polarization values. In addition, the reliability of the MOCVD PZTfilm is better than that generally obtained using other depositiontechniques, particularly with respect to imprint/retention.

[0072] Specifically, in one example, MOCVD PZT ferroelectric films aregrown in an Applied Materials 200 mm MOCVD Giga-Cap™ chamber integratedwith a liquid delivery system and vaporizer installed on a Centura™mainframe, as illustrated in FIG. 7. The baseline PZT film depositionparameters are described in Table PZT1 provided herein below, and thepreferred metalorganic precursors are detailed in Table PZT2, alsoprovided infra. Use of the pre-mixed precursor “cocktails” described inTable PZT2 provides enhanced repeatability and throughput relative tothe use of elemental precursor solutions. The precise composition andmolarity of the starting precursor solutions can be varied as needed.Use of pre-mixed “cocktails” permits hardware simplification since onlya single vaporizer is needed. Earlier processes employed multipleelemental precursors and required two vaporizers rather than thesimplified configuration shown in FIG. 7.

[0073] The preferred process sequence 208 proceeds as follows. After thewafers are delivered to the CVD chamber, the wafer sits on the lift pinsabove the wafer heater for about 30 sec (shorter times are alsopossible, for example, ˜5 sec to 30 sec). This allows the wafer topre-heat, avoiding thermal shock, which causes the wafer to break. Next,the wafer is lowered onto the wafer heater and the temperature isallowed to stabilize for about 60 sec. During these first two steps, themetalorganic precursors are sent directly to the vaporizer bypass line,bypassing the process chamber. PZT deposition begins once the precursorflow is diverted into the CVD chamber by opening the chamber valve andclosing the bypass valve. The process parameters shown in Table PZT1provide a deposition rate of approximately 160 Å/min. PZT depositionends when the precursors are sent back to the vaporizer bypass line.Following deposition, the wafer remains in the chamber for 5 sec withthe throttle valve open to evacuate the chamber before opening the slitvalve between chambers for removal. TABLE PZT1 Preferred processparameters for depositing PZT thin films by MOCVD. Heater Temperature640 to 650° C. Wafer Temperature ˜600 to 609° C. Pre-Deposition Time onChuck 30 sec on-pins/60 sec on-heater He B Carrier Flow Through 250 sccmVaporizer #1 He B Carrier Flow Through 250 sccm Vaporizer #2 Oxygen Flow1000 sccm Ar Purge Flow 250 sccm Ar Push Gas Pressure on Precursor 60psi Ampoules Vaporizer Temperature 190° C. Jackets/Lid/Feedthrough 190°C. Temperatures Showerhead to Heater Spacing 350 mils Chamber Pressure 4Torr Precursor #1 Flow (PZTG-2103) 65 to 82 mg/min Precursor #2 Flow(PZTG-2104) 118 to 135 mg/min Total Precursor Flow 200 mg/min Pb/(Zr +Ti) (in liquid) 1.00 to 1.14 Zr/(Zr + Ti) (in liquid) 0.40 DepositionRate 160 Å/min Substrate Ir (100 nm)/Si₃N₄/SiO₂/Si and IrO_(x) (50nm)/Ir (50 nm)/Si₃N₄/SiO₂/ Si

[0074] TABLE PZT2 Metalorganic precursors employed for CVD PZTdeposition. Precursors were purchased from Advanced Technology Materials(ATMI). Pb Zr Ti Conc Conc Conc Ampoule Precursor (Molar) (Molar)(Molar) #1 Pb(thd)₂-pmdeta, Zr(O- 0.090 0.090 0.135 iPr)₂(thd)₂, andTi(O- iPr)₂(thd)₂ in an octane-based solvent system (ATMI Product #:PZTG- 2103) #2 Pb(thd)₂-pmdeta + 0.205 0.045 0.066 Zr(O-iPr)₂(thd)₂ +Ti(O-iPr)₂(thd)₂ in octane-based solvent system (ATMI Product #:PZTG-2104)

[0075] In accordance with one example, the dependence of filmPb/(Zr+Ti)_(film) ratio and the Pb/(Zr+Ti)_(gas) ratio in the gas phaseis illustrated in FIG. 8. The process described in Table PZT1 providesthe characteristic plateau region in which the Pb composition in thefilm is self-correcting. Generally, the plateau region, an example ofwhich is shown in FIG. 8, is the processing regime that provides theoptimum PZT properties. Using the preferred process parameters in TablePZT1, the self-correcting plateau is observed between Pb/(Zr+Ti)_(gas)ratios of approximately ˜0.8 and 1.3 for a wafer temperature of about600° C. (heater set point temperature of about 640° C.). Within thiscomposition region, stoichiometric, single-phase, (111)-textured PZTthin films are obtained. The optimum physical and electrical propertiesare observed within the more narrow range of Pb/(Zr+Ti)_(gas)=1.00 to1.14, with a preferred ratio of 1.07.

[0076] In addition to the preferred process described above, lowertemperature processes may also be used for the PZT deposition step.Reducing the overall thermal budget simplifies capacitor integration,and depositing the PZT film is typically the highest temperature step.FIG. 9 shows the effect of reduced temperature on the size of theself-correcting Pb composition regime for the standard processconditions given in Table PZT1. It is evident in FIG. 9 that the size ofthe self-correcting plateau decreases significantly as the temperatureis reduced. The PZT films also become increasingly rough at lowtemperature. For a wafer temperature of about 587° C. (heater set pointof about 620° C.), the self-correcting behavior is no longer observedwhen the standard process conditions are used. As mentioned above, aself-correcting plateau is needed in order to obtain high quality PZTfilms and a robust process.

[0077] To reduce the deposition temperature and maintain a largeself-correcting plateau, the process pressure is reduced from about 4Torr to about 2 Torr and N₂O is added to the conventional O₂ oxidizergas stream (total oxidizer flow is kept constant). As shown in FIG. 10,for a wafer heater temperature of about 630° C., reduced pressurecombined with N₂O+O₂ gas flow significantly increases the size ofself-correcting plateau region relative to the standard process. Asimilar effect is shown in FIG. 11 for a wafer heater temperature of620° C. A range of pressures (1 to 10 Torr) and N₂O additions (10% to100%) may be used for the low temperature deposition processes. Twoexemplary processes are described in Tables PZT3 and PZT4, and theseprocesses provide the results shown in FIGS. 10 and 11, respectively.Using this approach, the wafer heater temperature can be reduced fromabout 640° C. to about 620° C., with a corresponding reduction in wafertemperature from about 600° C. to about 575° C. TABLE PZT3 Lowtemperature CVD PZT process #1. Heater Temperature 630° C. WaferTemperature ˜586° C. Pre-Deposition Time on Chuck 30 sec on-pins/60 secon-heater He B Carrier Flow Through 250 sccm Vaporizer #1 He B CarrierFlow Through 250 sccm Vaporizer #2 Oxygen Flow 500 sccm N₂O Flow 500sccm Ar Purge Flow 250 sccm Ar Push Gas Pressure on Precursor 60 psiAmpoules Vaporizer Temperature 190° C. Jackets/Lid/Feedthrough 190° C.Temperatures Showerhead to Heater Spacing 350 mils Chamber Pressure 2Torr Precursor #1 Flow (PZTG-2103) 82 to 115 mg/min Precursor #2 Flow(PZTG-2104) 85 to 118 mg/min Total Precursor Flow 200 mg/min Pb/(Zr +Ti) (in liquid) 0.79 to 1.00 Zr/(Zr + Ti) (in liquid) 0.40 DepositionRate ˜107 Å/min Substrate Ir (100 nm)/Si₃N₄/SiO₂/Si and IrO_(x) (50nm)/Ir (50 nm)/Si₃N₄/SiO₂/ Si

[0078] TABLE PZT4 Low temperature CVD PZT process #2. Heater Temperature620° C. Wafer Temperature ˜575° C. Pre-Deposition Time on Chuck 30 secon-pins/60 sec on-heater He B Carrier Flow Through 250 sccm Vaporizer #1He B Carrier Flow Through 250 sccm Vaporizer #2 Oxygen Flow 250 sccm N₂OFlow 750 sccm Ar Purge Flow 250 sccm Ar Push Gas Pressure on Precursor60 psi Ampoules Vaporizer Temperature 190° C. Jackets/Lid/Feedthrough190° C. Temperatures Showerhead to Heater Spacing 350 mils ChamberPressure 2 Torr Precursor #1 Flow (PZTG-2103) 82 to 115 mg/min Precursor#2 Flow (PZTG-2104) 85 to 118 mg/min Total Precursor Flow 200 mg/minPb/(Zr + Ti) (in liquid) 0.79 to 1.00 Zr/(Zr + Ti) (in liquid) 0.40Deposition Rate ˜96 Å/min Substrate Ir (100 nm)/Si₃N₄/SiO₂/Si andIrO_(x) (50 nm)/Ir (50 nm)/Si₃N₄/SiO₂/ Si

[0079] The top electrode 128, 130 is formed on the capacitor dielectric126, as illustrated at 210 of FIG. 4. In this embodiment of the instantinvention, the top electrode is comprised of two layers 128, 130,however, the top electrode can be implemented in just one layer.Preferably, the layer next to the PZT dielectric is comprised of iridiumoxide (preferably less than 100 nm thick—more preferably less than 50 nmthick and even more preferably less than 30 nm thick). Preferably, thelayer between the conductive oxide and top electrode diffusionbarrier/hard mask is comprised of iridium (preferably less than 100 nmthick—more preferably less than 50 nm thick and even more preferablyless than 20 nm thick).

[0080] In particular it is advantageous for Pb based ferroelectrics tohave a conductive oxide top electrode such as IrO_(x), RuO_(x), RhO_(x),PdO_(x), PtO_(x), AgO_(x), (Ba,Sr)RuO₃, LaSrCoO₃, LaNiO₃, YBa₂Cu₃O_(7-X)rather than a noble metal in order to minimize degradation due to manyopposite state write/read operations (fatigue). Many of the Biferroelectrics such as SBT can also use noble metal electrodes such asPt, Pd, Au, Ag, Ir, Rh, and Ru and still retain good fatiguecharacteristics.

[0081] If the top electrode is an oxide it is advantageous to have anoble metal layer above it in order to maintain low contact resistancebetween the top metal contact and oxide. For example, it is possiblethat a TiN in contact with IrOx might form TiO2 during subsequentthermal processes that is insulating. For any electrode using anexpensive noble metal such as Pt, Ru, Pd, or Ir it is advantageous froma cost and integration standpoint to use as thin of layer as possible.

[0082] For PZT electrodes (electrodes bounding a PZT dielectric), thepreferred top electrode stack is ˜20 nm Ir (130) deposited by PVD in Aron ˜30 nm IrOx (128) deposited by reactive PVD in Ar+O₂ on top of thePZT 126. IrOx is preferred to be deposited ˜500° C. in gas mixturesbetween 30% and 50% O2 with the rest oxygen with a relatively lowsputter power and hence slow deposition rate (preferred to be less than20 nm/min).

[0083] Preferably, the entire capacitor stack (220 of FIG. 5) ispatterned and etched at one time (preferably using a different etchantfor some of the layers), but each layer or grouping of layersalternatively may be etched prior to the formation of the subsequentlayer or layers. If multiple layers or all of the layers are etchedsimultaneously, then a hard mask layer (e.g., 132 of FIG. 3) is formedover the stack at 212 of FIG. 4. Preferably, the hard mask is thickenough and comprised of a material so as to retain its integrity duringthe etch process.

[0084] It is preferred that the capacitor be completely enclosed byconductive top and bottom diffusion barriers and an insulating sidewalldiffusion barrier. In some integration approaches it is preferred tohave a conductive diffusion barrier remain on top of the capacitor afteretching the entire capacitor. In all cases it is preferred to have acapacitor as short as possible for ease of integration.

[0085] Prior art hard masks 132 are composed of a single layer ofmaterial, typically a TiN layer or a TiAlN layer, which in some caseshas been left on top of the FeRAM capacitor stack after definitionthereof for subsequent use as a hydrogen barrier. Unfortunately, since abottom electrode diffusion barrier layer 122 may also be made of thesame material, a substantial portion of the hard mask 132 will beremoved during the etch of the bottom electrode diffusion barrier layer122, as illustrated in FIGS. 12 and 13.

[0086] Note that in FIG. 12, the hard mask 132 and the bottom electrodediffusion barrier 122 are the same material (e.g., TiAlN). Since thebarrier 122 is electrically conductive, the barrier must be removed inorder to electrically isolate neighboring FeRAM cells from one another.As the barrier layer 122 is etched, the hard mask 132 etches at the samerate, thereby causing a substantial reduction of the hard mask thicknessand a substantial rounding at the corners 131, as illustrated in FIG.13. Such corner rounding can lead to an exposure of the top electrode130 (e.g., an iridium layer) at the corners 131 that is undesirable forseveral reasons. First, such exposure may cause the top electrode 130 tocontaminate production tools during subsequent processing; in addition,since the exposed electrode 130 is not an effective hydrogen diffusionbarrier, the ferroelectric dielectric material 126 may experiencehydrogen contamination (for reasons described in greater detail below)that may degrade substantially the FeRAM performance.

[0087] One prior art solution is to further increase the thickness ofthe hard mask 132 to compensate for such loss during etch of the bottomelectrode diffusion barrier 122. Such a solution, however, undesirablyincreases the overall height of the FeRAM capacitor. In addition,through experiments it has been found that even with such compensation,a side portion of the underlying top electrode 130 (e.g., an iridiumelectrode) may still be subsequently exposed. Although a subsequentinsulative barrier (e.g., an AlOx film, not shown) will be depositedover the capacitor stack, the insulative barrier is relatively thin andis intended as a sidewall barrier, and thus does not cover the exposedtop electrode well after patterning thereof. Since the exposed portionof the top electrode 130 is not an effective barrier, the FeRAM is thennegatively susceptible to hydrogen exposure, thereby degrading theperformance thereof as described above.

[0088] In accordance with one aspect of the present invention, amulti-layer hard mask is disclosed in which a hard masking layeroverlies an etch stop layer. The etch stop layer is substantially moreselective than the overlying masking layer with respect to an etchemployed to remove the bottom electrode diffusion barrier layer.Therefore during an etch of the capacitor stack, an etch of the bottomelectrode diffusion barrier layer results in a substantially completeremoval of the hard masking layer. However, due to the substantialselectivity (e.g., 10:1 or more) of the etch stop layer with respect tothe overlying masking layer and bottom electrode diffusion barrier 122,the etch stop layer completely protects the underlying top electrode,thereby preventing exposure thereof. In addition, in accordance withanother aspect of the present invention, the etch stop layer iselectrically conductive and serves as a diffusion barrier, therebyeliminating a need for another diffusion barrier layer and reducing anoverall height of the FeRAM capacitor stack.

[0089] In accordance with one aspect of the present invention, a method212 (e g., of FIG. 4) of forming an FeRAM using a multi-layer hard maskis illustrated in FIG. 14, and designated at reference numeral 212.Initially, the capacitor stack layers are formed at 204, 206, 208 and210, as discussed previously, and comprise, for example, the bottomelectrode layer(s) 124, the ferroelectric dielectric layer 126, and thetop electrode layer(s) 128, 130. Subsequently, a multi-layer hard mask299 is formed thereover at 300, for example, by forming an etch stoplayer 302 at 304 of FIG. 14 followed by a masking layer 306 at 308, asillustrated in FIG. 15a. In accordance with one aspect of the presentinvention, the etch stop layer 302 comprises an electrically conductivematerial that has a substantially slower etch rate than the overlyingmasking layer 306 with respect to an etch chemistry employed to etch thebottom electrode diffusion barrier layer 122. For example, for a TiAlNmasking layer 306, the etch stop layer 302 comprises a TiAlON layer witha substantial amount of oxygen therein, and the benefits of such an etchstop layer 302 will be apparent in the subsequent discussion of themethod 212.

[0090] The method 212 then continues at 310, wherein a substantialportion of the capacitor stack is etched by patterning the multi-layerhard mask 299 and using the multi-layer hard mask to etch the underlyinglayers in the stack, for example, etching the top electrode layer(s)128, 130, the ferroelectric layer 126, and the bottom electrode layer(s)124. Note that the bottom electrode diffusion barrier layer 122 hasstill not been etched, and an etch of such layer must proceed since thelayer is electrically conductive and thus the exposed portion must beremoved in order to electrically isolate neighboring FeRAM capacitorstacks.

[0091] In accordance with the present invention, the bottom electrodediffusion barrier layer 122 has a composition substantially the same asthe masking layer 306, for example, TiAlN. Therefore, as the method 212proceeds to 312, an etch of the bottom electrode diffusion barrier layer122 results in a substantial or complete removal of the masking layer306 on top of the capacitor stack, as illustrated in FIG. 15b. Inaccordance with one exemplary aspect of the present invention, themasking layer 306 is sufficiently thin that an overetch of the barrierlayer 122 results in substantially all of the masking layer 306 beingremoved, thereby exposing the underlying etch stop layer 302.

[0092] As discussed above, an etch rate of the etch stop layer 302 issubstantially less than an etch rate of the overlying masking layer 306during the patterning of the bottom electrode diffusion barrier layer122. In the above manner, a substantial overetch of the barrier layer122 may be performed without an exposure of the top electrode layer 130(e.g., an iridium layer). In addition, by completely removing theoverlying masking layer 306 off of the capacitor stack, the total heightof the stack is reduced, which advantageously aids in subsequentintegration steps.

[0093] In accordance with one exemplary aspect of the present invention,an etch of the TiAlN barrier layer 122 and the TiAlN masking layer 306is performed using a chlorine etch chemistry. With such etch chemistry,an etch selectivity between the masking layer 306 and the underlyingTiAlON etch stop layer 302 is about 10:1 or more. Therefore when etchingthe barrier layer 122, once the etch removes the masking layer 306 andreaches the etch stop layer 302 on top of the capacitor stack, the etchslows down substantially, thereby allowing a substantial overetch of thebarrier layer 122. In addition, since the etch slows down substantially,the etch stop layer 302 completely protects the underlying top electrodelayer 130, thereby preventing an exposure of a side portion 131 thereof,as illustrated in FIG. 15b. Thus, the etch stop layer 302 is all thatremains of the multi-layer hard mask after the patterning of the bottomelectrode diffusion barrier layer 122.

[0094] Therefore, in accordance with one aspect of the presentinvention, a multi-layer hard mask 299 and a method 212 of forming anFeRAM using such a multi-layer hard mask is disclosed. In such asolution, the hard mask 299 is composed of two or more layers (302,306), wherein the top layer 306, the masking layer, acts as the hardmask and is removed as part of the capacitor stack etch process. Thesecond, underlying layer 302, the etch stop layer, acts as the topelectrode diffusion barrier and an etch stop during the capacitor stacketch. A third, optional layer (not shown) is an additional diffusionbarrier, and may be located between the etch stop layer 302 and theunderlying top electrode 130.

[0095] As discussed above, the top layer, the masking layer 306, may bethe same material as the bottom electrode diffusion barrier layer, forexample, TiAlN, however, such a solution is not required by the presentinvention. Rather, as long as the etch rate of the masking layer 306 isapproximately the same rate as the bottom electrode diffusion barrierlayer 122, any material may be employed and is contemplated as fallingwithin the scope of the present invention. For example, one may use aconductive nitride, carbide or carbo nitride as the masking layer.

[0096] Similarly, although TiAlON is disclosed as one exemplary etchstop layer, it should be understood that any material that exhibits ahigh selectivity with respect to the bottom electrode diffusion barrierlayer 122 (and the masking layer 306) may be employed and iscontemplated by the present invention. For example, an oxygen dopedmaterial may be employed as the etch stop. An oxide is a good etch stopusing the appropriate etch chemistries. It has been noted that Cl₂+BCl₃chemistries with quickly etch both materials yet Cl₂ or Cl₂+Archemistries only slowly etch the oxy-nitride films. Although addingoxygen to these materials will in general increase the resistivity,there is in general a window where the resistance is acceptable andwhere a large change in the etch characteristics can be obtained. Anestimate of the maximum resistivity for the etch stop layer 302 is about10 mΩ-cm.

[0097] In one example of the present invention, the multi-layer hardmask 299 is about 50 to 500 nm thick (more preferably around 100 to 300nm thick—most preferably around 200 nm thick). The hard mask 299thickness is controlled by the etch process and the relative etch ratesof the various materials, the thicknesses of the etched layers, theamount of overetch required, and the desired remaining etch stop layerthickness after etching all of the layers. Thinner ferro stack layerscan use thinner hard masks. The hard mask 299 may or may not be removedafter the etching of the capacitor stack. If the hard mask 299 is notremoved, then it is preferable to form the hard mask of a conductivematerial. However, a non-conductive or semiconductive material may beused, but the interconnection to the top electrode of the capacitorshould preferably be formed through this hard mask so as to make directconnection to the top electrode.

[0098] In accordance with an alternative aspect of the presentinvention, a single layer, pure oxide hard mask etch stop that isinsulating may be employed, but the etch process must then be adjustedin order to ensure that this layer is completely removed.

[0099] In accordance with one exemplary aspect of the present invention,the etch stop layer 302 also serves as the top electrode diffusionbarrier layer and comprises TiAlON having a film thickness of about 20nm or more and about 50 nm or less. In addition, the TiAlON has acomposition of oxygen that maintains the resistivity of the layer toabout 10 mΩ-cm or less. Alternatively, etch stop layer and the barrierlayer may comprise separate layers, for example, a TiAlON etch stoplayer having a thickness of about 15 nm or more and about 40 nm or less,with the etch stop layer overlying a TiAlN diffusion barrier layer (notshown) having a thickness of about 20 nm or more and about 40 nm orless.

[0100] In the preferred embodiment shown in FIG. 15a, the hard mask 299comprises a TiAlN masking layer 306 having a thickness of about 200 nmon top of a TiAlON etch stop layer 302 having a thickness of about 30 nmand a composition of about O 0.6, N 0.4. In addition, a separate barrierlayer (not shown) may comprise a TiAlN layer having a thickness of about30 nm.

[0101] In alternative preferred embodiment, the hard mask 299 is furthersimplified to two layers of TiAlN layer of about 200 nm thick on top ofa hard mask etch stop layer of TiAlON (composition (O 0.6 N 0.4)) andabout 40 nm thick where the TiAlON layer acts both as hard mask etchstop and also as conductive hydrogen diffusion barrier.

[0102] In another alternative aspect of the present invention, one mayemploy TiN and TiON as the masking layer and the etch stop layer/barrierlayer, respectively. These materials are advantageously because thematerials are relatively simple to deposit, have a low resistivity. Inparticular, the resistivity of TiO is not much higher than TiN andbecause of the higher oxygen it creates an excellent etch stop.

[0103] After the contact formation several different deposition stepshave been described. In particular, the formation of the bottomdiffusion barrier 122, bottom electrode 124, ferroelectric 126, topelectrode 128, 130 and hard mask 132, 299. It is likely that all ornearly all of these pieces of equipment will be considered potentiallycontaminated by ferroelectric elements. Therefore these pieces ofequipment may be considered dedicated. The wafers will most likely havea reasonable, if not a high contamination level on the backside of thewafers. The next process step after hard mask deposition is typicallylithography. It is likely that processing wafers with backsidecontamination through this tool will contaminate the tool and henceresult in contamination of clean wafers processed through this tool withFeRAM contaminants on their backside. Therefore it is preferred to cleanthe backsides of the FeRAM wafers in order to share the lithographyequipment and allow clean wafers to be processed through the lithographyequipment and not have any FeRAM contamination.

[0104] The clean process depends on the backside contamination elementsand their contamination levels. Assuming the preferred approach (PVDbarrier, hard mask, bottom electrode, top electrode and MOCVD PZT) therewill be low levels of Ir on the backside, but continuous films assumingthe MOCVD process does not have edge exclusion. Therefore for this typeof wafer contamination the preferred backside wafer clean process is awet etch process that etches the back, edges and small region on thefront side of the wafer near the edge. The etch process is somewhatdependent on the materials present on the backside of the wafer (forexample if it is Si, SiO₂ or Si₃N₄). As discussed earlier it ispreferred to have SiN present on the wafer backside because veryaggressive chemicals can be used to etch any ferro contamination whileminimizing the amount of SiN etched. An example of an aggressivechemical is hot 80° C. concentrated HF or a bath chemistry that combineshot aqua regia (HCl+HNO₃) or SC₂ (HCl+H₂O₂) with HF. Instead of usingperoxide dissolved ozone can be used and can be even more effective. TheSiN also has a slow diffusion rate of these materials and hence only asmall amount of SiN needs to be removed in order to have surfaces soclean that there are no detectable levels of ferro elements.

[0105] It is preferred to perform pattern and etch the capacitor stackwith only one lithography step. This is not only cheaper but also allowsthe cell size to be smaller by eliminating misalignment tolerances thatare necessary if more than one lithography step is used.

[0106] It is preferred that patterning process is by lithography and thetype of lithography is dependent on the desired size of the feature sizeplus the misalignment to underlying layer (CONT in this example). Inthis particular example, the lithography was performed using DUV (248nm) lithography process using organic BARC and relatively thin resist.Larger features could use i-line or even g-line features while evensmaller features would require even smaller wavelengths 193 nm or 157nm. Instead of an organic BARC an inorganic BARC could also be used andthis might be incorporated into the hard mask etch process. The resistthickness is chosen such that it can hold up during the hard mask etchprocess. In this example the resist was 510 nm thick while the hard maskwas 260 nm thick, the BARC thickness was 60 nm and 248 nm lithographywas used to pattern capacitors ˜250-600 nm in size with a gap spacing of180 to 300 nm narrow space between the capacitors. Wider spaces werealso printed depending on cell size and shape.

[0107] As mentioned before the preferred approach is to use a hard maskwith multiple etch processes. These etch process can be modified byusing elevated temperatures in order to achieve even steeper sidewallslopes and therefore less CD growth. In general it is preferred tominimize CD growth and this can be achieved by having steeper etchprofile or by having thinner layers.

[0108] The first step is etching the hard mask and any BARC at 212 ofFIG. 4 (inorganic or organic) that might be used followed by clean/ashprocesses. In this preferred embodiment the BARC/hard mask is preferablyetched in the same chamber using a one or more step etch recipe. Ingeneral, the preferred etch system is has a high density plasma. In thisexample, two steps are used. The BARC etch consisted of Cl₂+O₂ at lowpressures (3 mTorr) at temperatures low enough not to damage the resist(60° C.) with high density plasma (300 W RF source power) and small bias(50 W RF on the chuck). An example of a tool of this type is the AMATDPS etch tool. After a short gas purge step the multi-layer Ticontaining hard mask stack is etched in Cl₂+BCl₃ gas chemistry (BCl₃substantially helps etching of O containing compounds present as cruston surface or as in this example O containing layers) at sametemperature as BARC etch (60° C.) at low pressure (5 mTorr) and highplasma density (1400 W source power) and still low bias (100 W RF onchuck). The exact process is adjusted to minimize CD growth, maximizeuniformity and repeatability of etch process while trying to minimizehard mask thickness.

[0109] After the hard mask is etched it is necessary to ash the resistand if the resist process leaves a residue, a clean is sometimes used(either before or after the ash) in order to remove this residue. Theash process can be performed either in a separate chamber/process tool,in situ in the hard mask etch tool or in situ in the ferro stack etchchamber. The clean can either be wet or dry and might be something assimple as DI dunk/rinse or possibly use more active chemicals such assolvent (EKC for example). The goal of the clean is to remove particlesand residue. In this specific example, an O₂ ash step (alternativelyO₂+H₂O or even fluorine containing compounds could be used) at elevatedtemperatures in order to enhance the ash rate (250° C.) using highplasma density, but low energy and little if any substrate bias (AMATASP chamber, for example). In order to try to remove the need for a wetclean process a more aggressive ash process can be used such as addingfluorine compounds such as CF₄ to the ash process and adding a smallamount of substrate bias.

[0110] In general it is preferred to etch as many layers in the samechamber as possible. Since the top electrode and bottom electrode aretypically hard to etch materials and usually very similar materialsthere is a strong preference to etch this ferro stack (top electrode,ferroelectric and bottom electrode) in the same etch chamber. Thefollowing discussion assumes that one etch chamber is used, to etch thisferro stack at 212 of FIG. 4 because that is preferred, but it is alsopossible to use multiple chambers which has the advantage that eachchamber can be optimized for each process.

[0111] The top electrode 128, 130 is etched after patterning the hardmask. In order to etch noble metal top electrodes (preferably Ir/IrOx) ahigh temperature etch process is used because this is typically neededin order to achieve a chemical etch. The chemical etch has the advantagethat steeper sidewall profiles can be achieved with usually less CDgrowth and better etch selectivity to other layers such as the hardmask. One exemplary etch chemistry for these noble metal electrodes isCl₂+O₂ or Cl₂+CO. Other gas additives such as N₂ or Ar can also be addedalthough Ar in particular is-usually not a good choice because it onlyetches by physical mechanisms and not chemical. An exemplary process issensitive to electrode and hard mask material. In this exemplaryembodiment the top electrode etch is Cl₂+O₂+N₂. For Ti containing hardmasks the oxygen content of the top electrode etch preferably is >5-10%in order to achieve a very low hard mask etch rate (e.g., goodselectivity to the hard mask). The optimum etch process uses a highdensity plasma (1200 W, for example) and an intermediate substrate bias(300 W chuck) at intermediate pressures (10 mTorr) and elevatedtemperatures (350-400° C.). This type of process results in etch ratesin the range of about 80 nm/min.

[0112] In general there is a tradeoff between physical etching using alarger substrate bias (lower pressure or higher chuck power) with theadvantage of a faster etch rate and chemical etching which in generalhas the advantage of a steeper capacitor profile, less CD growth andbetter selectivity to the hard mask. The gas composition can beoptimized to provide the maximum chemical etch rate or the maximum ratioof chemical etch rate to physical etch rate. This difference can beestimated by measuring etch rate as a function of temperature andphysical etch rate is temperature independent while the chemical etchrate varies with temperature. A rough estimate of this maximum chemicaletch component based on gas composition (varies depending on details ofprocess) is roughly 30-80% O₂ or CO for Cl₂+O₂ and Cl₂+CO, respectively.Another important aspect of the etch process is the time between cleans.

[0113] One reason to maximize the chemical nature of the etch process isin reducing CD growth. When using these Ti containing hard masks and Ocontaining etch chemistries it has been determined that Ti etched fromthe edges of the hard mask by physical etching can redeposit on thesides of neighboring capacitors resulting in deposition of oxygencontaining material that causes CD growth of the capacitor. The physicaletching causes the formation of facets on the sides of the capacitor. Ingeneral, larger facet formation results in larger CD growth and largerCD growth is correlated to larger facet formation.

[0114] Etching these materials in general results in re-deposition ofnoble electrode and other low vapor pressure materials on the walls ofthe etch chamber. These layers can cause problems such as particlegeneration or variation in the etch process. Therefore the time betweencleans indicates the number of wafers that can be etched before one ofthese problems becomes severe enough that the chamber has to be cleanedand conditioned for further etching. It has been found that this timebetween cleans can be impacted by the choice of etch chemistry plus manyother factors including preconditioning, choice of wall materials andtemperature plus details of the physical design of the etch tool itselffor example.

[0115] Etching the ferroelectric 126 requires choosing an etch processthat is again compatible with the choice of hard mask. For a PZTferroelectric material, multiple etch approaches will be discussed.

[0116] The first exemplary approach uses a modification of the hard masketch based on a Cl₂+Fluorine gas+oxidizer (O₂ or CO for example) with Aror N₂ possibly added as well. For high temperature etching the fluorinegas prevents chemical undercut of the PZT. It turns out that fluorinegas at an elevated substrate temperature (350° C., for example) canchemically etch at least part of the PZT. Using fluorine containinggases that also contain hydrogen helps reduce this effect, for exampleCF₄>CHF₃>CH₂F₂>CH₃F. An exemplary etch condition using this etchapproach is Cl₂+O₂+CH₂F₂ (75/35/12) at high chuck temperature (350°C.-400° C.) at medium pressure (10 mTorr) at high density plasma (1200W) and large substrate bias (450 W RF on chuck). These types ofprocesses result in etch rates in the range of 70 nm/min. If theferroelectric film is rough a large overetch is in general needed.

[0117] In analyzing the above PZT etch that contain fluorine components,the inventors of the present invention discovered problems with theetched PZT layer. In particular, it was noted that various defects wereidentified in the PZT layer, for example, void or gaps therein, in somecases as large as 1 μm or more. In addition, some spacing ordelamination could periodically be identified between the PZT layer andthe underlying bottom electrode layer. Such defects are undesirablebecause they may result in degraded polarization properties, forexample, the switch polarization. It is believed that the cause of suchfilm degradation is the fluorine component(s) within the PZT etchchemistry. More particularly, it is believed that fluorine isselectively chemically attacking elemental portions of the PZT withinthe film as opposed merely to its exposed sidewall edges of the stack.For example, from a thermodynamics point of view, when fluorine isexposed to zirconium oxide, it reacts to form zirconium fluoride andoxygen since that result is energetically preferred.

[0118] Therefore the inventors of the present invention determined thatthe fluorine component of the PZT etch should be eliminated to avoid thePZT degradation highlighted above. In accordance with one aspect of thepresent invention, the PZT portion of the capacitor stack etch employsBCl₃ as opposed to an etch chemistry containing a fluorine component.The use of BCl₃ as an etchant for the PZT is not an obvious substitutionfrom the prior art etch chemistry for at least the following reasons.Initially, BCl₃ does not appear viable because such an etch providespoor selectivity with respect to the hard mask (e.g., a TiAlN hardmask), thereby resulting in substantial hard mask erosion. Oneconventional way to improve the selectivity of a layer with respect tothe hard mask is to add oxygen, however, BCl₃ is extremely reactive; somuch so that the boron and chlorine may disassociate due to the oxygenand negatively form gas phase particles. Therefore initially one ofordinary skill in the art would not be motivated to use a BCl₃ etchchemistry to etch the PZT.

[0119] The inventors of the present invention discovered that at lowchuck temperatures, if you lower the bias, the hard mask erosion due tothe BCl₃ slows, but the PZT etch rate also slows. Surprisingly, however,it was discovered that while the low bias was maintained, if the chucktemperature was increased, the PZT etch rate increased substantiallywithout any substantial change in the hard mask etch rate. Therefore ata generally low bias of about 100-150 W, a high temperature BCl₃ etchwill provide an effective etch of PZT with acceptable selectivity to thehard mask without any introduction of oxygen. Generally a temperature ofabout 150° C. or more is acceptable and preferably a temperature ofabout 350° C. is employed.

[0120] In addition, it was found that at lower temperatures, forexample, about 150° C., a higher bias was needed to etch the PZT (e.g.,about 250 W), however, the lower the temperature, the poorer theselectivity is to the hard mask. As the temperature was increased, thebias could be lowered and higher selectivities were obtained. Forexample, at a temperature of about 350° C., a bias of about 100-150 Wwas employed and excellent selectivity to the hard mask was obtained.

[0121] Further, it was found by the inventors of the present inventionthat adding Ar to the BCl₃ during the PZT etch could be employed to anadvantage. For example, at lower temperatures (e.g., around 150° C.),only enough Ar to generate and maintain the plasma is used. For example,the ratio of Ar to BCl₃ in such an example is about 20-30% Ar. At highertemperatures, for example, about 350° C., a ratio of about 50/50facilitates hard mask selectivity.

[0122] Therefore according to one aspect of the present invention, a PZTetch approach uses a BCl₃ etch chemistry which may further include Ar.The BCl₃ etch chemistry is effective in etching oxide materials becausethe B reacts with the oxygen in the oxide forming BOx which is etched byCl. The metals in the oxide can then easily react with Cl₂ formingvolatile compounds. For Ti containing hard masks, the optimum hard maskfor purposes of selectivity is a nitride (e.g., TiAlN) because the Breacts with the nitride to form a BN layer which slows the etch rate.

[0123] One issue with using this etch chemistry with oxygen containingchemistries in preceding or subsequent etch steps is to ensure thatthere is a purge step between these steps in order to prevent the oxygenfrom those etch chemistries from reacting with the BCl₃. Because of thereactive nature of this etch gas, low substrate biases can be used(100-200 W RF on the chuck) along with possibility of higher pressures(10-30 mTorr). Etch rates of 50-100 nm/min are achievable with thesetype of conditions. These low biases also result in less physicaletching of the hard mask although if a surface layer of oxide is on theTi hard mask due to reaction from the oxygen in the top electrode etchit will be removed.

[0124] As discussed above, use of a BCl₃ etch for the PZT etch resultsin a capacitor stack etch of, for example, Ir/PZT/Ir using Cl₂+O₂+N₂ forthe top/bottom electrodes and BCl₃+Ar for the PZT with each etchperformed at a relatively high temperature (e.g., about 350° C.). Theabove etch methodology allows for a quality PZT layer without anysubstantial gap or void degradation. Upon evaluating the resultingetched FeRAM capacitor stack, however, it was noticed that conductivematerial in some cases would tend to form on side edges of theferroelectric PZT layer. It is believed that such conductive materialcomprises etched iridium that re-deposits on the sidewall of the PZTduring the etch of the iridium bottom electrode layer. Further, uponanalysis, it was appreciated by the inventors of the present inventionthat such re-deposition of iridium on the PZT sidewall edges occursbecause of the substantially vertical PZT sidewall.

[0125] The BCl₃ PZT etch results in a substantially vertical sidewallhaving an angle of about 89 degrees or more. Generally, such a verticalprofile is considered highly desirable in order to minimize the criticaldimension (CD) of the FeRAM capacitor. It was discovered, however, thatwith such a steep profile, when iridium from the etched bottom electrodelayer re-deposits on the PZT sidewall, less ion impingement occursthereon. Therefore due to the steep PZT sidewall profile caused by theBCl₃ PZT etch, re-deposited iridium does not tend to be removed by ionimpingement during the bottom electrode etch. Since the re-depositediridium is electrically conductive, such re-deposition disadvantageouslyresults in capacitor leakage and in some cases a “shorting out” of theFeRAM capacitor.

[0126] It was discovered by the inventors of the present invention thatby lowering the etch temperature during the PZT etch, a slightly slopedor non-vertical PZT sidewall edge profile may be obtained. At low etchtemperatures (e.g., about 60° C.), however, BCl₃ does not etch wellbecause of poor selectivity to the hard mask, and because the etch isextremely slow, and in some cases may completely stop.

[0127] The inventors of the present invention therefore appreciated thata PZT etch that generates an intentionally sloped or non-vertical PZTsidewall profile provides for a resulting stack without substantialleakage or potential shorted capacitor problems. Introducing anintentional sloped PZT sidewall profile in the capacitor stack iscounter-intuitive because generally attempts are made to achieve purelyvertical sidewalls to minimize the capacitor critical dimension.According to one aspect of the present invention, a sloped PZT profilehaving a sidewall angle of about 88 degrees or less is generated using alow temperature etch process (e.g., about 60° C.) using a fluorinegas+Cl₂+an oxidizer, for example. Therefore in accordance with thepresent example, the capacitor stack process comprises a hightemperature etch for the top electrode, a low temperature etch for thePZT, and a high temperature etch for the bottom electrode. Such aprocess can be employed in a single etch tool using two separatechambers associated therewith, wherein the top and bottom electrodeetches are performed in one of the chambers at the high temperature(e.g., about 350° C.), and transferred to and from a second chamber inwhich the PZT layer etch is performed at a lower temperature (e.g., 60°C.).

[0128] As discussed above, the BCl₃ PZT etch does not work well at lowtemperatures, however, the inventors of the present invention discoveredthat by using a fluorine gas+Cl₂+an oxidizer with Ar or N₂ at lowtemperatures, a sloped PZT profile having an angle of about 88 degreesor less could be achieved. More particularly, in one example,CHF₃+Cl₂+O₂+N₂ was used at a temperature of about 60° C. on chuck.Unexpectedly, unlike at high temperatures (as discussed earlier), suchan etch chemistry does not cause voids or gaps in the PZT and thus asloped PZT sidewall profile is obtained without PZT film degradation.

[0129] In accordance with one aspect of the present invention, a PZTsloped profile has an angle of about 80 degrees or more and about 88degrees or less. In the above manner, the slope is sufficiently angledto allow ion impingement (e.g., chlorine ions) to remove re-depositediridium on the PZT sidewall (during bottom electrode etch) at a fasterrate than the deposition. Concurrently, by preventing the angle frombecoming too small, critical dimension growth is minimized.

[0130] After removal of the PZT layer, the bottom electrode layer ispatterned. Etching the bottom electrode 124 typically uses an etchprocess very similar to the top electrode etch process if the electrodematerials are similar as is the situation in this preferred embodiment.Note that with a Ti hard mask the bottom electrode etch will effectivelystop on the bottom electrode diffusion barrier 122 (TiAlON, TiAlN orTiON in this example). This is an advantage of this approach because itallows large overetch to be used without the formation of undesirablerecesses or notching next to ferro structures because of overetch.

[0131] After etching the bottom electrode 124, one option is to performan oxygen anneal in order to replace any oxygen that might have beenremoved by the etch process. One way to perform this anneal is anin-situ O₂ plasma (1000 W) with minimal (25 W chuck) at 20 mTorr in thehigh-T etch chamber or possibly run the wafers through a standard ashprocess (250° C.). The ash process could be O₂ or possibly O₂+H₂Ocombination.

[0132] In general, the various etch steps are end pointed using opticalemission spectroscopy, substrate bias changes, or some other techniquesuch as RGA or optical techniques that look at the wafer surface.Depending on the details of the etch process, roughness of the layersbeing etched and the shapes and especially spaces in the structuresbeing etched it is typically necessary to set larger overetch times thanmight be expected based on endpoint traces. This is because the etchrate in narrow spaces is slower than in tight spaces plus rough filmslike frequently found with MOCVD PZT need more etch time in order toclear. Another reason to increase the overetch time is to remove “feet”that are present for some processes at the bottom of the ferro stack.

[0133] The etch process is a dirty process and hence it is likely thatthe etch tool and the front side, edge and backside of the wafers willhave FeRAM contamination or have etch residues with FeRAM contamination.It is therefore desirable to clean the front side of the wafer andchemically remove etch residues and possibly remove a thin layer ofdamaged PZT. This post capacitor etch wet clean can with some etchconditions and chemistries, be as simple as a DI water clean (tank soakwith or without megasonic followed by a spin rinse dry) or the tank etchmight be acid based in order to improve the clean or remove more damage.One exemplary acid solution might be similar to SC1 or SC2 (possiblywithout peroxide but maybe with ozone), for example (NH₄F+O₃+H₂O orNH₄F+H₂O₂+HCl+H₂O: 1/1/1/300) in order to also assist in particleremoval plus metal contamination removal). The backside and edges of thewafer are likely to be significantly contaminated by re-deposition ofFeRAM elements. The contamination is preferably removed prior to processin a shared tool. One method to remove the backside chemistry is to usea specialized tool such as a backside clean tool (e.g., as made by SEZ).Even hard to etch materials such as Ir can be removed if they are submonolayer coverage by undercutting the etching of the material on thebackside. Processes as described previously can be used here.

[0134] One option is to anneal the ferroelectric stack in order toremove etch damage. The preferred thermal budget of this anneal is ˜600°C. for 2 min. One option for this anneal is to perform the anneal with aPb overpressure in order to prevent Pb loss that might damage theferroelectric. Methods to achieve this Pb overpressure include furnaceanneal with the capacitor facing Pb compound such as PbO or maybe PbTiO3or even PZT. Another method is to anneal while flowing very low amountsof Pb metalorganic with oxygen such that the Pb forms PbO but does notdeposit as such on the wafer because its deposition rate is slower thanits evaporation rate.

[0135] As shown in the method of FIG. 4, once the post-etch clean 250has been completed, an insulating sidewall diffusion barrier (typicallyAlOx) is deposited at 260 in order to protect the FeRAM capacitor fromhydrogen contamination, and also to protect other structures from leadcontamination if the ferroelectric dielectric is PZT. In prior artsolutions, the sidewall diffusion barrier was formed over the capacitorstack after the bottom electrode diffusion barrier 122 was etched toelectrically isolate neighboring capacitor stacks from one another. Theinventors of the present invention discovered that such a solution wasundesirable since some sidewall diffusion barrier layer materials (e.g.,AlOx) are not substantially selective with respect to the underlyinginterlayer dielectric 112, typically SiO₂. Therefore, in prior artmethods, when subsequently etching the sidewall diffusion barrier, theunderlying SiO₂ layer would also be attacked. In addition, if either thehard mask (e.g., the etch stop layer 302) or the bottom electrodediffusion barrier layer comprise TiAlON, for example, and havesufficient oxygen content therein, the AlOx etch would also attack suchlayers and in some cases compromise the top/bottom barrier capability ofsuch layers. Accordingly, the inventors of the present invention,appreciating the problems of the prior art, disclose a method offabricating an FeRAM by forming the sidewall diffusion barrier layerover the capacitor stack before the etching of the bottom electrodediffusion barrier layer. Such a method results in several advantagescould be achieved, as will be discussed in greater detail below.

[0136] Turning to FIG. 16, a method 260 of forming the sidewalldiffusion barrier layer in accordance with one aspect of the inventionis provided. At 262, a sidewall diffusion barrier layer 300, forexample, AlOx is formed over the capacitor stack 301 and the exposedportion 304 of the bottom electrode diffusion barrier layer 122, asillustrated in FIG. 17. In one example, the sidewall diffusion barrier300 comprises AlOx having a thickness of about 8 nm or more and about120 nm or less. More preferably, the AlOx barrier layer 300 has athickness of about 10 nm or more and about 20 nm or less. Alternatively,other materials such as Ta₂O₅, AlN, TiO₂, ZrO₂, HfO₂, or any stack orcombination thereof may be employed and are contemplated as fallingwithin the scope of the present invention.

[0137] In one exemplary aspect of the present invention, the sidewallbarrier 300 comprises a multi-layer with two possible materials, thefirst material being AlOx or one of the materials highlighted above, andthe second layer comprising SiN or AlN. The sidewall diffusion barrier300 primarily needs to prevent reaction between the PZT ferroelectriclayer 126 and the interlayer dielectric (ILD) 112, 134. Another use asenvisioned here is as part of the hydrogen diffusion barrier. It iscurrently planned to have complete protection of the capacitor tohydrogen during subsequent processing by the use of hydrogen diffusionbarriers on all sides. For example, the TiAlN or TiAlON used as part ofthe hard mask 302, 306 and as the bottom electrode diffusion barrier 122are conductive hydrogen barriers (since the capacitor will need to makeelectrical contact to and from the top/bottom electrodes) while the AlOxis an insulating hydrogen diffusion barrier (in order to prevent the topand bottom electrodes from shorting out the capacitor). For theexemplary process described herein, the AlOx is used as a Pb and Hdiffusion barrier while the Si₃N₄ that is deposited later on in the flowis used as a contact etch stop. In the subsequent text, AlOx will beused, however, it should be understood that other sidewall diffusionbarrier materials may instead be used.

[0138] The primary reason for deposition at this point (prior to etchingthe bottom electrode diffusion barrier) is to make the AlOx etch processmore simple. Other alternatives include, for example: AlOx etch backafter PZT deposition which is helpful for physical bottom electrode etchprocesses, AlOx etch back after etching bottom electrode diffusionbarrier which has advantages in limiting CD growth of this layer, but isa harder etch to develop, and no AlOx etch back but instead the AlOx isetched as the last part of the via etch process. In the subsequentdiscussions it is also assumed that a via etch stop layer (typically SiNbut might possibly be SiC, for example) will be deposited prior to thedeposition of interlayer dielectric.

[0139] In accordance with one exemplary aspect of the present invention,a process for depositing the AlOx sidewall diffusion barrier layer ischemical vapor deposition (CVD) (e.g., MOCVD, CVD or atomic layerdeposition), but other approaches such as sputter deposition can also beused. The primary advantage of the CVD approaches is better stepcoverage along the sidewalls 308 of the capacitor stack 302, which isdesirable to ensure an effective sidewall barrier 300. Since what isimportant is the thickness after etch-back of the AlOx on the sides 308of the capacitor, a better step coverage dramatically reduces the planarthickness on top 310 of the capacitor stack and over the exposed portion304 of the bottom electrode diffusion barrier layer 122 that needs to bedeposited and etched. PVD deposition of the sidewall diffusion barrier300 will work and one such exemplary deposition process is depositionusing a pure Al target in an Ar+O₂ gas using a pulsed DC or an RF powersupply.

[0140] Returning to FIG. 16, the sidewall diffusion barrier 300 residingon the top 310 of the capacitor stack 301 and over the exposed portions304 of the bottom electrode diffusion barrier 122 (between neighboringstacks) is etched at 264, as illustrated in FIG. 18. The AlOx etch backprocess needs to remove the AlOx from planar surfaces 305, 310, but notfrom the sidewalls 308 of the capacitors. It is therefore important tominimize the overetch of the AlOx, yet it is still necessary that theAlOx clears over the diffusion barrier layer 122 between neighboringcapacitor stacks in order for a complete subsequent etching of thebottom electrode diffusion barrier layer 122, in order to preventneighboring capacitors from shorting out each other (since the bottomelectrode diffusion barrier layer is electrically conductive).

[0141] A conformal AlOx deposition process makes this much easier toachieve especially for a high aspect ratio ((>1) capacitor height tocapacitor-to-capacitor space). According to one exemplary aspect of thepresent invention, the etch chemistry for etching the AlOx sidewalldiffusion barrier is BCl₃+Ar. The BCl₃ is effective in etching the AlOxwith a good selectivity to the underlying nitride hard mask 306 on top310 of the capacitor stack (e.g., TiAlN) and nitride bottom electrodediffusion barrier 122 (e.g., TiAlON with small oxygen content) between304 the neighboring capacitor stacks. The Ar may be added (as in theabove example) to the etch chemistry because the resulting surface (of atop portion of the hard mask and the bottom electrode diffusion barrier)is smoother, but one disadvantage is that it etches AlOx on the slopedsides 308 of the capacitor; that is, the etch is less anisotropic. Anexemplary etch process uses a high density plasma etch tool such as aAMAT DPS at near room temperature (˜60° C.) with ˜50% Ar at anintermediate gas pressure (˜10 mTorr) 750 W remote plasma power and lowbias (e.g., 150 W RF on chuck). The etch rate is 50 nm/min under thistype of etch process.

[0142] This type of etch process would potentially cause problems if theetch back was performed after etching the TiAlN bottom electrodediffusion barrier because it quickly etches SiO₂ because this is also anoxide. However, in accordance with the present invention, since the AlOxsidewall diffusion barrier etch is performed prior to the etch of thebottom electrode diffusion barrier 122, no such problem occurs.

[0143] In addition, the BCl₃ etch is substantially selective withrespect to the underlying nitride layers (the hard mask 306 and thebottom electrode diffusion barrier layers 122). The aluminum-oxygenbonds in the AlOx layer are extremely strong, however, the boron in theBCl₃ reacts with oxygen to break the aluminum-oxygen bonds. The chlorinein the BCl₃ then reacts with the aluminum to remove the AlOx. After theAlOx is removed, the boron in the BCl₃ reacts with nitrogen in theunderlying nitrides to form boron nitride, which slows down subsequentetching. Therefore, one can perform a substantial overetch of the AlOxsidewall diffusion barrier layer without substantially impacting thenitrides underneath (e.g., TiAlN or TiAlON (low content O) masking layer306 or bottom electrode diffusion barrier 122). This is particularlyhelpful with regard to the bottom electrode diffusion barrier layer 122since it allows the AlOx to be completely removed thereover, thusensuring that all of the underlying barrier 122 is exposed for removalin a subsequent etch process, and thus ensuring that the neighboringcapacitor stacks 301 are electrically isolated from one another.

[0144] Using the same chamber the bottom electrode diffusion barrier isnow etched at 266 of FIG. 16, as illustrated in FIG. 19. The chemistry,in one example, is changed to Cl₂+Ar which effectively etches TiAlN orTiAlON (low oxygen) (masking layer 306 and barrier 122), but has goodetch selectivity to AlOx on the sidewalls 308 and to the TiAlON (high O)hard mask etch stop layer 302. The Ar etch gas component in oneexemplary aspect of the present invention, is added to help achieve asmooth post etch surface although the disadvantage is an increase in theAlOx etch rate on the sidewalls of the capacitor stack(s). An exampleetch process uses a high density plasma etch tool such as a AMAT DPS atnear room temperature (˜60° C.) with ˜50% Ar at an intermediate gaspressure (˜10 mTorr) 1000 W remote plasma power and low bias (e.g, 100 WRF on chuck). The etch rate is 100 nm/min under this type of etchprocess.

[0145] It is common that the thickest part of the masking layer 306 isthicker than the bottom electrode diffusion barrier. Therefore the etchtime and endpoint traces may be adjusted for this. This situation willtherefore show up on the endpoint trace and also will result inreasonably large overetch on the W/TiN and SiO₂ under the capacitors.Fortunately the etch chemistry does not attack these materials very fastexcept for the TiN, and the Ar keeps this attack to a minimum becausethe TiN is only present as a thin diffusion barrier between the Wcontacts and SiO₂ dielectric. One problem that has been observed tooccur during this etch was the undercut of the bottom electrodediffusion barrier 122 if it was TiAlN. By the addition of a small amountof oxygen during the TiAlN deposition process (as discussed surpa), theundercut of the TiAlON barrier 122 was for practical purposeseliminated. Another issue with this etch is that a reasonable amount ofoveretch is necessary in order to completely remove the TiAlN from abovethe hard mask etch stop layer 302. The TiAlN layer, when not completelyremoved, is very rough and will be difficult to make contact to duringvia formation because of SiN step coverage on the rough TiAlN.

[0146] In the discussion of the capacitor stack etch, the sidewalldiffusion barrier etch and the bottom electrode diffusion barrier etchabove, the accompanying figures illustrate such etches as ideallyanisotropic, resulting in generally vertical sidewall profiles. Suchsidewall illustrations, however, do not occur in typical processing, butare provided for ease of illustration and to illustrate other featuresof the present invention with simplicity and clarity. Instead, the aboveetches are not ideally anisotropic, and the actual capacitor stack crosssection does not exhibit perfectly vertical sidewalls, but ratherexhibits generally sloped stack sidewalls, as illustrated in FIG. 20. InFIG. 20, the capacitor stack (hard mask 302, 306, top electrode layer128, 130, ferroelectric dielectric layer 126, and bottom electrode layer124) has been etched with the bottom electrode diffusion barrier layer122 remaining and the patterned sidewall diffusion barrier 300 on thesidewalls 308 of the stack.

[0147] As discussed above, it is desirable to remove the sidewalldiffusion barrier layer 300 off of the top 310 of the capacitor stackand in the areas 304 between the stacks, however, it is desirable forthe sidewall diffusion barrier 300 to remain on the stack sidewalls 308in order to protect the ferroelectric dielectric 126 in the stack fromhydrogen contamination. Because the capacitor stack is not perfectlyvertical and since the etch thereof has a chemical component, thesidewall diffusion barrier layer 300 on the sidewalls 308 does getetched to some degree, and often it is desirable to analyze thecapacitor stack after the sidewall barrier etch to ensure that thebarrier 300 still covers the capacitor stack sidewalls 308. Because theremaining sidewall layer 300 may be relatively thin (e.g., about 150-200Angstroms), analyzing the sidewall layer 300 is difficult, for example,requiring an expensive and laborious TEM (transmission electronmicroscopy) analysis.

[0148] The inventors of the present invention discovered that if thethickness of the masking layer 306 is sufficiently thick, during thecapacitor stack etch, although rounding will be experienced at thecorners 400 thereof, the sidewall diffusion barrier layer 300 willoverlie such corners 400 upon its deposition, as illustrated in FIG. 20.Subsequently, during the etch of the masking layer 306 portion of thehard mask (which will typically be done concurrently with an etch of thebottom electrode diffusion barrier layer 122), a portion 402 of thesidewall diffusion barrier layer 300 overlying a corner portion 404 ofthe masking layer 306 will protect such portion 404 of the masking layer306 from being etched, thereby resulting in “ears” 406 being formed ontop of the hard mask etch stop layer 302, as illustrated in FIG. 21.Note, however, if a thickness of the sidewall diffusion barrier layer300 is not sufficiently thick, no portion 402 will overlie the maskinglayer 306, and consequently no “ears” will form.

[0149] Therefore by evaluating a capacitor stack after the etching ofthe masking layer 306, identification of the “ears” 404 will allow oneto quickly ascertain that the sidewall diffusion layer 300 is adequatelycovering the capacitor stack sidewalls 308. The “ears” 406 are easy todetect (by a standard or tilt scanning electron microscope (SEM), forexample), and their presence indicates that the sidewall barrier 300(e.g., AlOx) is above the height of the hard mask etch stop diffusionbarrier 302. A lack of “ears” 406, although not indicative of a lack ofsidewall barrier coverage, does indicate that the sidewall barrier maynot be sufficiently thick, and may warrant further analysis or a processchange.

[0150] Therefore the thicknesses of the hard mask, AlOx deposition andetch back process and bottom electrode diffusion barrier etch backprocess are all adjusted to ensure that ears are observed because thiseasy to detect feature proves that AlOx protection is successfully inplace.

[0151] Therefore in accordance with one aspect of the present invention,a method of ascertaining whether a sidewall diffusion barrier issufficiently thick after patterning thereof is disclosed.

[0152] It is necessary to protect the ferroelectric material fromhydrogen used by the rest of the semiconductor process. Many of thestandard semiconductor processing steps contain hydrogen, for example,SiN deposition, HDP SiO₂ deposition using silane, CVD W deposition,forming gas anneal plus many others. Another problem is that only a fewmaterials are hydrogen barriers, for example, SiO₂ is not. Hydrogenbarrier materials include many nitrides such as TiN, TiAlN, AlN and SiNand AlOx. Ferroelectric electrode materials such as Ir or Pt are noteffective barriers. Pt in particular is known to catalyze reaction of H₂to H that appears to be much worse for ferroelectric properties.

[0153] Therefore in order to have complete hydrogen protection it isnecessary to have complete protection from hydrogen (top, bottom andsides). In this disclosure the TiAlN or TiAlON is used as a hydrogenbarrier on the top and bottom while AlOx is used on the sides of thecapacitor. Complete protection requires not having any small gaps orseams between the various layers. Additional protection comes from theSiN except that the SiN deposition step frequently contains hydrogen soa hydrogen barrier is typically needed before this process as well.

[0154] Although the AlOx etch-back is the primary approach of thisdisclosure there are other alternatives that also achieves these goals.The alternative approach the TiAlON bottom electrode diffusion barrieris etched immediately after etching the bottom electrode. This etch caneither be performed at high T or low T although it is preferred thatthis be done at low T (<200° C.). The preferred etch chemistry for thisutilizes a short BCl₃ containing (may contain Ar and/or Cl₂ as well)etch step followed by Cl₂+Ar etch as described previously. After poststack etch clean the AlOx followed immediately by deposition of theinterlayer dielectric that may or may not include separate etch stoplayer (typically SiN or SiC). One possibility is that the AlOx can beused as an etch stop by appropriate changes in the via etch chemistry.

[0155] The last step of the via etch is now etching AlOx. The preferredetch chemistry for this process is still BCl₃+Ar and it is desirable tominimize the amount of overetch that is needed. If a hydrogen diffusionbarrier is next deposited in the via such as TaN or TiN as is typical instandard semiconductor processing then it might be possible to simplifythe ferroelectric stack. By using this approach it is possible to removethe top and bottom electrode diffusion barrier or else to use materialsthat are not hydrogen barriers. The reason is that the hydrogenprotection from the top comes from the AlOx plus the via barrier. Thesetwo layers also protect the capacitor from additional hydrogen from thebottom although it might be necessary to adjust the previous processesto prevent them from supplying hydrogen later on that without a bottomelectrode hydrogen barrier degrade the capacitor properties.

[0156] It is recommended that after this etch step that the wafers becleaned. Since no ferroelectric elements are deliberately exposed atthis point, the primary purpose of this wet clean is to remove halogens(Cl) left on the surface from the etch which otherwise might causecorrosion problems and also to remove any particles left on the surface.The suggested chemistry for this process is therefore a DI H₂O or adilute SC1 type of chemistry. For particle removal the use of amegasonic or other such tool can also be used to promote particleremoval.

[0157] At the beginning of the AlOx deposition process the front side ofthe wafer has exposed FeRAM elements. The AlOx deposition process may ormay not result in contamination of the tool (defined to be addition ofFeRAM contaminants on subsequent wafers at levels above care about level(˜10¹⁰ atoms/cm²). If the AlOx deposition process on FeRAM wafers doesnot result in contamination then it is preferred to wet clean thebackside of the wafer prior to depositing this sidewall diffusionbarrier. If the AlOx deposition process on FeRAM wafers does result intool contamination then instead of performing a backside wafer clean theclean after stack etch, the backside clean can be done after AlOx etchback/bottom electrode diffusion barrier etch step. One option is toanneal the capacitor at this point. One reason to do this anneal so soonis that if a low-K layer is chosen then it might not be compatible withthe preferred PZT damage recovery anneal condition (600° C. 2 min).

[0158] The preferred next step is the deposition of a via etch stopmaterial. Example films are silicon nitride, silicon carbide, (SiCNO) oran silicon oxide (preferably a high-density plasma oxide). This etchstop layer is needed primarily because the via etch is reaching twodifferent via depths. The etch stop makes simple means in order to etchtwo via depths without the large overetch on the thinner via causing aproblem. The other advantage the etch stop has is that the SiN etch canbe tuned to be selective to underlying materials (W, TiN and SiO₂). Thisprevents forming narrow grooves when a via is misaligned to theunderlying contact. Forming these grooves is a particular reliabilityproblem by making a thin spot in the via diffusion barrier especiallyfor Cu vias. The etch stop thickness is chosen based on the via etchprocess.

[0159] Another advantage of having the etch stop is that it preventsmisaligned vias that fall off the capacitor from shorting the capacitor.In a similar manner it allows vias placed close to the capacitor to bemisaligned and still not short the capacitor. This behavior allows theFRAM bit cell size to be reduced by allowing a reduced via to capacitorspace than if the etch stop was not present. The typical depositionprocess for the SiN would be PECVD using SiH₄ and N₂ or NH₃. It ispreferred to use SiH₄ and N₂ in order to create a low H SiN barrier. Ifthere is a worry that the AlOx sidewall protects all of the PZT, but notthe electrode then it is recommended that a no hydrogen SiN process beused such as PECVD using SiCl₄ and N₂ or alternatively a very low T SiNprocess be used such as SiH₄ and N₂ using special low T PECVD such asECR SiN. Another no hydrogen option is a PVD SiN barrier.

[0160] The preferred next layer is deposition of gap fill dielectricsuch as HDP SiO_(2.) With the SiN deposited the gaps between capacitorare very narrow and the aspect ratio is quite large. Therefore a gapfill dielectric is recommended. Another example of a gap fill dielectricis spin on glass. Although not desirable small voids between narrowcapacitor space might be tolerated but voids where stacked vias for BLconnection will be made will cause problems.

[0161] On top of this layer is the primary interlevel dielectric, asillustrated at 270 of FIG. 4, and possible material choices are Sio₂,FSG, PSG, BPSG, PETEOS, HDP oxide, a silicon nitride, siliconoxynitride, silicon carbide, silicon carbo-oxy-nitride , a lowdielectric constant material (preferably SiLK, porous SiLK, teflon,low-K polymer (possibly porous), aerogel, xerogel, BLACK DIAMOND, HSQ,or any other porous glass material), or a combination or stack thereof.

[0162] After the deposition of the interlayer dielectric it is preferredto planarize the dielectric. The preferred method is chemical mechanicalplanarization (CMP) although other methods such as spin on dielectricsor deposition and etch back. CMP is preferred as it results in globaland not just local planarization. The CMP planarization will thin thedielectric to a workable thickness above the capacitor. Preferred valuesare between 300 nm to 500 nm. The surface after CMP needs to be asplanar as possible.

[0163] Vias now need to be formed to make electrical connection to thetop electrode and to contacts. Standard semiconductor processingtechniques are used for this process. The via etch needs to etch throughall of the dielectrics to the etch stop without etching through the etchstop because the vias have two different heights. Next the etch stopneeds to be etched without etching a significant amount of theunderlying material (W, TiN and SiO₂ at the contacts) and hard mask etchstop layer (TiAlON or TiON) on top of the capacitors under a fewpreferred embodiments. SiN etch processes with these characteristicshave been developed and the etch selectivity to TiAlON has beendocumented to be very good. This result is useful since the SiN etchrate on the capacitor is expected to faster and the SiN is also expectedto be thinner compared to at the contacts which is deeper.

[0164] After the via etch, it is recommended that an anneal of theinstant invention is performed, as illustrated at 280 of FIG. 4, so asto remove damage introduced by the capacitor stack processing (such asthe ferroelectric material etch, encapsulation, and contact etch) intothe capacitor dielectric and to improve the electrical properties ofthese features. If this anneal is not done at this point (i.e. if theanneal is done with the PZT stack exposed on its sidewalls), then it mayresult in the loss of Pb near the perimeter of each capacitor. This lossin Pb in the PZT film will result in the degradation of the electricalproperties of small capacitors (capacitors with large perimeter to arearatios) after the capacitor integration.

[0165] The anneal of the instant invention is, preferably, performedafter the interlevel dielectric is formed and the via holes patternedand etch, but prior to the filling of the vias with the conductivematerial. The anneal conditions, for example, are: around 400 to 800° C.(more preferably around 500 to 700° C.—most preferably around 600° C.)for a duration of around 30 seconds to 5 minutes (more preferably foraround 1 to 4 minutes—most preferably around 2 minutes) in an inert gas(N₂, Ar) atmosphere or vacuum. After this anneal is performed, the viadiffusion barrier (liner) and conductor are formed using standardsemiconductor processing techniques. The conductor is either W with TiNdiffusion barrier or more preferably Cu with TaN, TaSiN, Ta, TiN, WN, orTiSiN diffusion barrier deposited by enhanced sputter deposition or morepreferably CVD. The Cu is deposited by first depositing a Cu seed byenhanced sputter deposition or CVD preferably followed by Cuelectroplating in order to fill the via. A standard semiconductorprocessing approach after the deposition of the metal in the via is toremove the metal on the top surface by etch back (W) or CMP (W and Cu).

[0166] Another alternative is that metal layer above the via is formedusing dual damascene process along with the via. The disadvantage ofthis approach is substantial increase in process complexity.

[0167] Although the invention has been shown and described with respectto a certain aspect or various aspects, it is obvious that equivalentalterations and modifications will occur to others skilled in the artupon the reading and understanding of this specification and the annexeddrawings. In particular regard to the various functions performed by theabove described components (assemblies, devices, circuits, etc.), theterms (including a reference to a “means”) used to describe suchcomponents are intended to correspond, unless otherwise indicated, toany component which performs the specified function of the describedcomponent (i.e., that is functionally equivalent), even though notstructurally equivalent to the disclosed structure which performs thefunction in the herein illustrated exemplary embodiments of theinvention. In addition, while a particular feature of the invention mayhave been disclosed with respect to only one of several aspects of theinvention, such feature may be combined with one or more other featuresof the other aspects as may be desired and advantageous for any given orparticular application. Furthermore, to the extent that the term“includes” is used in either the detailed description or the claims,such term is intended to be inclusive in a manner similar to the term“comprising.”

What is claimed is:
 1. A method of etching a capacitor stack associatedwith a ferroelectric memory cell, comprising: forming a bottom electrodelayer, a PZT ferroelectric layer, a top electrode layer, and a hard masklayer over a substrate; patterning the hard mask layer; patterning thetop electrode layer in accordance with the patterned hard mask;patterning the PZT ferroelectric layer using a BCl₃ etch at asubstantially high temperature in accordance with the patterned hardmask; and patterning the bottom electrode layer in accordance with thepatterned hard mask.
 2. The method of claim 1, wherein patterning thePZT ferroelectric layer comprises using a BCl₃ etch at a temperature ofat least 150° C.
 3. The method of claim 2, wherein patterning the PZTferroelectric layer comprises using a BCl₃ etch at a temperature ofabout 350° C., wherein the patterning of the PZT layer is substantiallyselective with respect to the patterned hard mask.
 4. The method ofclaim 3, further comprising adding Ar to the BCl₃ etch of the PZTferroelectric layer, wherein a ratio of BCl₃ to Ar comprises about 1:1.5. The method of claim 2, further comprising adding Ar to the BCl₃ etchof the PZT ferroelectric layer, wherein a ratio of BCl₃ to Ar comprisesabout 20% Ar or more and about 30% Ar or less.
 6. A method of forming acapacitor stack in a ferroelectric memory cell, comprising: forming abottom electrode layer, a PZT ferroelectric layer, a top electrodelayer, and a hard mask layer over a substrate; patterning the hard masklayer; patterning the top electrode layer using a Cl₂+O₂ or a Cl₂+COetch in accordance with the patterned hard mask; patterning the PZTferroelectric layer using a BCl₃+Ar etch at a temperature of about 150°C. or more in accordance with the patterned hard mask; and patterningthe bottom electrode layer using a Cl₂+O₂ or a Cl₂+CO etch in accordancewith the patterned hard mask.
 7. The method of claim 6, whereinpatterning the top electrode layer, the PZT ferroelectric layer and thebottom electrode layer is performed at a temperature of about 350° C. ormore.
 8. The method of claim 6, wherein the hard mask layer comprisesTiAlN, and wherein an oxygen content in the Cl₂+O₂ or the Cl₂+CO etch ofthe top and bottom electrode layers is at least about 5%, therebyproviding a substantial etch selectivity of the capacitor stack withrespect to the patterned TiAlN hard mask.
 9. The method of claim 8,wherein the temperature of the BCl₃+Ar PZT ferroelectric layer etch isabout 350° C., thereby providing a substantial etch selectivity of thePZT ferroelectric layer with respect to the patterned TiAlN hard mask.10. The method of claim 9, wherein a ratio of BCl₃ to Ar in the PZTferroelectric layer etch comprises about 1:1.
 11. The method of claim 6,wherein a ratio of BCl₃ to Ar in the PZT ferroelectric layer etchcomprises about 20% Ar or more and about 30% Ar or less.
 12. A method offorming a capacitor stack in a ferroelectric memory cell, comprising:forming an iridium bottom electrode layer, a PZT ferroelectric layer, aniridium top electrode layer, and a TiAlN hard mask layer over asubstrate; patterning the TiAlN hard mask layer using a BCl₃ etch;patterning the iridium top electrode layer using a Cl₂+O₂ or a Cl₂+COetch in accordance with the patterned hard mask, wherein an oxygencontent in the iridium top electrode layer etch is at least about 5%,thereby providing a substantial etch selectivity with respect to theTiAlN hard mask; patterning the PZT ferroelectric layer using a BCl₃+Aretch at a temperature of about 150° C. or more in accordance with thepatterned hard mask, wherein the temperature of about 150° C. or moreprovides for an etch of the PZT ferroelectric dielectric layer that issubstantially selective with respect to the TiAlN hard mask; andpatterning the bottom electrode layer using a Cl₂+O₂ or a Cl₂+CO etch inaccordance with the patterned hard mask, wherein an oxygen content inthe iridium bottom electrode layer etch is at least about 5%, therebyproviding a substantial etch selectivity with respect to the TiAlN hardmask.
 13. The method of claim 12, wherein patterning the PZTferroelectric layer comprises using the BCl₃+Ar etch at a temperature ofat about 350° C.
 14. The method of claim 13, wherein a ratio of BCl₃ toAr comprises about 1:1.
 15. The method of claim 12, wherein thetemperature of the PZT ferroelectric layer etch is about 150° C., andwherein a ratio of BCl₃ to Ar comprises about 20% Ar or more and about30% Ar or less.
 16. A method of etching a capacitor stack associatedwith a ferroelectric memory cell, comprising: forming a bottom electrodelayer, a PZT ferroelectric layer, a top electrode layer, and a hard masklayer over a substrate; patterning the hard mask layer; patterning thetop electrode layer in accordance with the patterned hard mask;patterning the PZT ferroelectric layer, wherein a resulting PZTferroelectric sidewall edge has a profile having an angle of less thanabout 88 degrees; and patterning the bottom electrode layer inaccordance with the patterned hard mask, wherein the PZT profile angleof less than about 88 degrees causes a re-deposition rate of bottomelectrode material on the PZT sidewall edge during the bottom electrodelayer patterning to be less than a removal rate thereof due to ionimpingement, thereby preventing bottom electrode material from formingon the PZT ferroelectric layer sidewall during the capacitor stack etch.17. The method of claim 16, wherein patterning the PZT ferroelectriclayer comprises etching using a fluorine gas+Cl₂+an oxidizer at arelatively low temperature.
 18. The method of claim 17, wherein thetemperature of the PZT ferroelectric layer etch is about 60° C.
 19. Themethod of claim 17, wherein etching the PZT ferroelectric layercomprises using a CHF₃+Cl₂+O₂+N₂ at a temperature of about 60° C. 20.The method of claim 16, wherein patterning the top and bottom electrodelayers comprise etching with a Cl₂+O₂ or a Cl₂+CO at substantially hightemperature, and wherein patterning the PZT ferroelectric layercomprises etching using a fluorine gas+Cl₂+an oxidizer at a relativelylow temperature.
 21. The method of claim 20, wherein the substantiallyhigh temperature comprises about 350° C., and the relatively lowtemperature comprises about 60° C.
 22. The method of claim 16, whereinthe sidewall edge profile angle of the PZT ferroelectric layer is about80 degrees or more.